Sampling control loop for a receiver for digitally...

Details Sampling control loop for a receiver for digitally... Sampling control loop for a receiver for digitally...

1998-09-25

2002-11-05

Corrielus, Jean (Department: 2631)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

Reexamination Certificate

active

06477215

ABSTRACT:

FIELD OF INVENTION
This invention relates to a sampling control loop for a receiver for digitally transmitted signals which are transmitted as symbols by quadrature modulation.
BACKGROUND OF INVENTION
Such transmission methods are known by the following abbreviations: FSK (=Frequency Shift Keying), PSK (=Phase Shift Keying), BPSK (=Binary Phase Shift Keying), QPSK (=Quadrature Phase Shift Keying), and QAM (=Quadrature Amplitude Modulation). The receiver circuits for these methods are known in the art and, as a rule, are similar in construction. An important constituent is the analog or digital sampling control loop, which ensures that the information of the digitally transmitted signals is sampled at the correct instant. The optimum sampling of these signals is temporally closely connected with the symbols of the transmitted data stream and is independent of whether the processing at the receiver end is analog or digital.
If the processing is digital, the digitization rate must, of course, be at least as high as the data rate of the transmitted symbols. As a rule, the digitization rate is well above this value, e.g., by at least one order of magnitude, with the digitization rate being free-running or locked to the symbols rate.
In an article by Floyd M. Gardner, “A BPSK/QPSK Timing-Error Detector for Sampled Receivers”, IEEE Transactions on Communications, Vol. COM-34, No. 5, May 1986, pages 423 to 429, it is described in detail how to timing errors can be determined from the respective symbols. To eliminate these timing errors, use is made of a sampling control loop, which is not described in detail. This control loop includes a timing error detector and a timing error corrector whose output is fed back to the sampling stage.
WO 96/11526 discloses a sampling control loop for a circuit for receiving digitally transmitted signals in which the digitization takes place after the quadrature demodulator by means of two analog-to-digital converters. The control loop changes the frequency and phase of the digitization clock, whereby the sampling instants for the symbols are optimally adjusted.
WO 96/17459 discloses a sampling control loop for a circuit for receiving digitally transmitted signals in which the digitization takes place before the quadrature demodulation. The digitization rate is independent of the rate and phase of the received symbols. In this embodiment, the optimum sampling instant for the respective symbol is formed by a digital interpolation circuit (“digital resampler”).
The known advantages of digital coding and transmission by means of symbols are that the transmission path and the receiver contribute no additional interference or noise to the signal content as long as the symbols are reliably recognized at the receiver end. The recognizability of the individual symbols is impaired by superimposed interference and noise signals which blur the originally punctiform symbol location in the vector diagram into an areal phase and amplitude range. If, in addition, the sampling instant for the individual symbols differs from the nominal value, reliable symbol recognition is no longer ensured under unfavorable receiving conditions.
The above disadvantages in the reception or evaluation of digitally transmitted signals relate to operating conditions which are no longer worthy of reception for conventional receiver circuits. Starting from this prior art, it is object of the invention to make the receiving circuit even less sensitive to interference.
SUMMARY OF INVENTION
A sampling control loop for a receiving circuit for receiving digitally transmitted signals, including a timing error detector for determining respective timing error values by which current symbol sampling instants differ from optimum symbol sampling instants given by the Nyquist criterion, wherein the timing error detector comprises an evaluating device coupled thereto which determines a reliability value from signals of the receiving circuit and controls the sampling control loop in accordance with the reliability value.


REFERENCES:
patent: 4827515 (1989-05-01), Reich
patent: 4896334 (1990-01-01), Sayar
patent: 5862191 (1999-01-01), Moridi

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