Sampling clock synchronization

Pulse or digital communications – Spread spectrum – Direct sequence

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Details

375118, 375120, 370103, 331 1A, 331DIG2, H04L 700

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active

048151092

ABSTRACT:
In a method for compensating for differences in a first clock signal's rate and a second clock signal's rate, transmitting voice samples from a first location synchronized to the first clock signal are received at a second location having a second clock for generating the second clock signal. The first clock signal and the second clock signal are compared to determine when a slip of one cycle has occured and it is determined which of the first and second clock rates is greatest. At the second location, the process includes adding a received voice sample for each predetermined number of slips which occur if the second clock is running too fast relative to the first clock, and discard an additional voice sample for each predetermined number of slips which occur if the second clock is running too slow relative to the first clock.

REFERENCES:
patent: 3580499 (1971-05-01), Bauer
patent: 3742145 (1973-06-01), Clark et al.
patent: 3867579 (1975-02-01), Colton et al.
patent: 3938086 (1976-02-01), Valbonesi
patent: 4528521 (1985-07-01), Grimes
patent: 4580279 (1986-04-01), Kahn
patent: 4592050 (1986-05-01), Bensadon
patent: 4672299 (1987-06-01), Grimes et al.
patent: 4737971 (1988-04-01), Lanzafame et al.
"A Cycle-Slip Detector for Phase-Locked Demodulators", Gardner, IEEE Transactions on Instrumentation, vol. IM-26, No. 3, Sep. 1977, pp. 251-254.

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