Sampling clock phase correction circuit of video signal

Details Sampling clock phase correction circuit of video signal Sampling clock phase correction circuit of video signal

1986-09-29

1987-12-15

Groody, James J.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358158, 358264, 340814, H04N 504

Patent

active

047136901

ABSTRACT:
A sampling clock phase correction circuit of video signal to keep stably a phase of a sampling clock to an image signal. A delayed signal of a video sync signal is employed for a reference signal of a sampling clock generation circuit. The delay quantity of the video sync signal is controlled to sample stably the video image signal according to the comparison and discrimination of a phase relation between a sampling clock signal and a video sync signal by a phase detection circuit and a CPU circuit. A precise phase correction where a characteristic change of circuit elements by a temperature drift or the like is compensated can be attained even for a high frequency video signal exceeding 100 MHz.

REFERENCES:
patent: 3637936 (1972-01-01), Krause
patent: 4631600 (1986-12-01), Fukui
IEEE Transactions on Broadcasting, vol. BC-17, No. 1, "A New Technique for Time-Base Stabilization of Video Recorders"; by Coleman, Mar. 1971, pp. 29-36.

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