Sampling clock generating circuit for A-D conversion of a variet

Details Sampling clock generating circuit for A-D conversion of a variet Sampling clock generating circuit for A-D conversion of a variet

1991-02-11

1992-12-01

Kostak, Victor R.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358158, H04N 704

Patent

active

051683601

ABSTRACT:
A sampling clock generating circuit generates a sampling clock which is used for the A-D conversion of a video signal. A master clock produced by a frequency synthesizer is demultiplied in frequency at dividing ratio N.sub.S by a programmable frequency demultiplier which is reset by the horizontal sync signal. The resulting sampling clock can have one of various frequencies depending on the combination of the frequency dividing ratio N.sub.M of the frequency synthesizer and the frequency dividing ratio N.sub.S of the programmable frequency demultiplier, so that it is fit for various video signals.

REFERENCES:
patent: 4751565 (1988-06-01), Emmons et al.
patent: 4757264 (1988-07-01), Lee et al.
patent: 4772950 (1988-09-01), Furuhata et al.
patent: 4779132 (1988-10-01), McBeath et al.
patent: 4827341 (1989-05-01), Akimoto et al.
patent: 4996596 (1991-02-01), Hirao et al.
patent: 5008751 (1991-04-01), Wischermann
patent: 5019907 (1991-05-01), Murakoshi et al.
Patent Abstracts of Japan, vol. 6, No. 81, May 19, 1982 and JP-A-57 20 074 Feb. 2, 1982.

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