Sampling clock correction circuit

Details Sampling clock correction circuit Sampling clock correction circuit

1978-10-19

1981-04-21

Safourek, Benedict V.

Pulse or digital communications

Repeaters

Testing

375102, 375103, 375118, 364724, H03K 5159, H04L 2508

Patent

active

042636710

ABSTRACT:
A circuit for maintaining proper sampling timing in a data modem wherein main channel equalizer error is correlated with a derivative channel signal to drive a clock correction signal. The derivative channel signal is derived from an equalizer using fewer coefficients than required to derive the main channel equalized signal, and calculation of the equalized derivative and clock correction signal is performed only once every other Baud.

REFERENCES:
patent: 4028626 (1977-06-01), Motley et al.
patent: 4071827 (1978-01-01), Koike et al.
patent: 4146840 (1979-03-01), McRae et al.

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