Sampling circuit, phase reference detecting circuit and sampling

Details Sampling circuit, phase reference detecting circuit and sampling Sampling circuit, phase reference detecting circuit and sampling

1995-03-21

1996-07-09

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Phase shift by less than period of input

327 91, 327158, 327271, H03H 1116

Patent

active

055348076

ABSTRACT:
A sampling circuit is not susceptible to an influence of structural components and environmental changes. A phase difference detecting circuit (5) detects a deviation of a sampling clock (.phi.2) from optimal sampling timing and outputs a phase difference signal. On the other hand, a phase reference signal (ORG) which is used as a reference to determine a phase advance and a phase lag is generated by a phase reference detecting circuit (4). In accordance with these signals, a sampling clock shifting circuit (2) shifts the sampling clock (.phi.2) so that the sampling clock (.phi.2) is activated at optimal sampling timing. Sampling is performed in accordance with such a sampling clock (.phi.2), whereby a basic signal is generated from which the phase reference signal (ORG) and the phase difference signal (i.e., an equivalent signal (EQU) and a non-equivalent signal (UPDN)) are generated. By means of feedback control, the sampling clock is automatically activated at optimal sampling timing.

REFERENCES:
patent: 4061977 (1977-12-01), Motley et al.
patent: 4232399 (1980-11-01), Heiter
patent: 4845390 (1989-07-01), Chan
patent: 4862014 (1989-08-01), Myers et al.
patent: 5179303 (1993-01-01), Searles et al.
patent: 5204559 (1993-04-01), Deyhimy et al.
patent: 5394024 (1995-02-01), Buckenmaier et al.
"PLL Applied Technique", pp. 149-150, Shigeharu Takamatsu, Jan. 20, 1989.

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