Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
2001-09-20
2003-05-20
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S091000
Reexamination Certificate
active
06566917
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a sampling circuit and an amplification type solid-state imaging device.
Conventionally, as an amplification type solid-state imaging device that employs a sampling circuit, there has been a known one in which each pixel element is provided with an amplification function for to read an optical reception signal by means of a scanning circuit. In particular, there have been energetically developed APS (Active Pixel Sensor) type image sensors having a CMOS type pixel element construction that is advantageous for the element to be integrated with a peripheral drive circuit and a signal processing circuit. In this APS type image sensor, it is required to form a photoelectric conversion section, an amplification section, a pixel selection section and a reset section within one pixel element, and normally three to four MOS transistors (T) are employed besides the photoelectric conversion section constructed of a photo diode (PD).
FIG. 5
shows the construction of the pixel element in the case of a PD+3T system. In
FIG. 5
, signal charges generated in a photoelectric conversion section
101
are converted into a voltage and applied to the gate of a transistor
102
. This transistor
102
executes impedance conversion (current amplification), and a signal V
sig
is read via a pixel selection switch
103
to the gate of which a voltage &phgr;x is applied. In the middle of the read period of this signal V
sig
, the potential of the photoelectric conversion section
101
is reset to a power voltage V
D
by a reset transistor
104
to the gate of which a voltage &phgr;R is applied. Therefore, a potential (optical reception signal) corresponding to the signal charges and a reset potential (reference signal) are read as a pair into the signal V
sig
.
The pixel section of the amplification type solid-state imaging device that employs the pixel element shown in
FIG. 5
can be expressed by a schematic diagram as shown in FIG.
6
. In
FIG. 6
is shown a pixel section
131
for executing the photoelectric conversion, amplification, read and reset. The read of the pixel section
131
is controlled by a voltage &phgr;
X
of a signal line
106
, and the reset of the pixel section
131
is controlled by a voltage &phgr;
R
of a signal line
107
. Thus, the amplified signal V
sig
is outputted from the pixel section
131
via a vertical signal line
108
.
FIG. 7
is a schematic diagram of an amplification type solid-state imaging device (two-dimensional image sensor) constructed by employing the pixel section
131
. In
FIG. 7
, a two-dimensional pixel region
140
is constituted of the pixel section
131
, a first vertical scanning circuit
141
and a second vertical scanning circuit
142
. The read operation of the pixel section
131
is controlled by a signal
143
from the first vertical scanning circuit
141
, and the reset operation is controlled by a signal
144
from the second vertical scanning circuit
142
. An output signal from the pixel section
131
is read by a vertical signal line
145
and thereafter transferred to a correlated double sampling circuit provided for each vertical signal line
145
. A differential signal representing a difference between the optical reception signal obtained during read and a reference signal obtained after the reset is outputted from the correlated double sampling circuit. With regard to the differential signal, variations in the threshold value between the pixel sections
131
are canceled, so that a fixed pattern noise (hereinafter referred to as FPN) of each pixel section
131
is suppressed. It is to be noted that the correlated double sampling circuit is constituted of a clamping circuit (clamping capacitor
146
and clamping switch
147
) and a sample hold circuit (sample hold switch
148
and sample hold capacitor
149
).
In the aforementioned correlated double sampling circuit, the vertical signal line
145
is connected to the sample hold switch
148
via the clamping capacitor
146
and connected to the clamping potential V
CP
via the clamping switch
147
.
FIGS. 8A through 8G
show the operation timing of the aforementioned correlated double sampling circuit. In the clamping circuit (clamping capacitor
146
and clamping switch
147
), the operation of clamping to the clamping potential V
CP
is executed by making a pulse &phgr;
C1
have high level during read of the optical reception signal (S
1
) from the pixel section
131
, and a differential signal V
sj
of a difference between the optical reception signal (S
1
) from the pixel section
131
and the reference signal (S
2
) is outputted from the clamping capacitor
146
. The sample hold switch
148
samples the differential signal V
sj
of the difference between the optical reception signal and the reference signal. Then, the signal V
sj
from the sample hold switch
148
is held by the sample hold capacitor
149
and amplified by an amplifier circuit
155
. The signal amplified by the amplifier circuit
155
is outputted as an output signal V
sr
to the horizontal signal line
164
via a horizontal selection switch
156
controlled by an output line
161
from the horizontal scanning circuit
160
, and differential signals V
sj
, V
sj+1
, . . . from the sample hold circuits are successively read. It is to be noted that the reference numeral
165
denotes a second constant current load of the amplifier circuit
155
. Finally, the signal V
sr
becomes a signal OS by the operation of a buffer amplifier
169
.
As described above, in the amplification type solid-state imaging device shown in
FIG. 7
, the FPN due to the variations in the threshold value between the pixel sections
131
is suppressed by the correlated double sampling circuit provided for each vertical signal line
145
. However, in the amplification type solid-state imaging device, the amplifier circuits
155
of the vertical signal lines
145
are accompanied by variations in the offset level, gain and so on. These variations, which are random in the horizontal direction and common in the vertical direction of an image, cause a significant FPN of a vertical stripe pattern in a video image, significantly impairing the image quality.
Accordingly, as a method for resolving the FPN of a vertical stripe pattern described above, the present applicant has proposed an amplification type solid-state imaging device as shown in
FIG. 9
(Japanese Patent Application No. 2000-49505). It is to be noted that this amplification type solid-state imaging device is described for better understanding of the present invention and is neither a known technology nor a prior art.
In this amplification type solid-state imaging device, the two-dimensional pixel region has the same construction as that of the two-dimensional pixel region
140
shown in
FIG. 7
, and neither of figures nor description for the two-dimensional pixel region is provided. Furthermore, in order to explain only the essential point, description is started from the output side of the clamping circuit with the detailed concrete circuit omitted.
In the case of
FIG. 7
, an output from the clamping circuit is only the differential signal V
sj
of the difference between the optical reception signal and the reference signal with respect to the clamping potential V
CP
that serves as a reference. This signal is sampled once by the sample hold circuit (sample hold switch
148
and sample hold capacitor
149
) and transferred to the amplifier circuit
155
. On the other hand, a differential signal V
sj
(a) of the difference between the optical reception signal and the reference signal is read to the output side of the clamping circuit, and thereafter a reference signal V
sj
(b) is further read in the case of FIG.
9
. The clamping potential, which is usually selected as this reference signal, serves as a reference for the differential signal V
sj
(a) and is common to the columns.
FIGS. 10A through 10F
are timing charts showing the timing of the signals of the aforementioned amplification type solid-state imaging
Conlin David G.
Dike Bronstein, Roberts & Cushman IP Group, Edwards & Angell, LL
Sharp Kabushiki Kaisha
Tucker David A.
Wells Kenneth B.
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