Sampling and holding circuit for signal having low sampling resi

Details Sampling and holding circuit for signal having low sampling resi Sampling and holding circuit for signal having low sampling resi

1988-10-03

1989-07-04

Zazworsky, John

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307358, 35821316, H03K 500, G11C 2702

Patent

active

048453820

ABSTRACT:
The circuit comprises a first sampling/holding circuit, to the input of which is applied the signal to be sampled, a second sampling/holding circuit identical to the first sampling circuit, to the input of which is applied a level of direct electrical voltage, and a differential amplifier coupled by a first input to the output of the first sampling/holding circuit and by a second input to the output of the second sampling/holding circuit. The first and second sampling/holding circuits are controlled with the same control pulses so that the sampled signal given at the output of the differential amplifier is a pure signal rid of the interference sampling signals given by the first sampling/holding circuit.

REFERENCES:
patent: 3851260 (1974-11-01), Colin
patent: 3965368 (1974-10-01), Emmons
patent: 4283742 (1979-09-01), Izumita et al.
patent: 4287441 (1981-09-01), Smith
Electronic Engineering, vol. 48, No. 577, mars 1976, pp. 47-49, Londres, GB; R. C. Tozer: "Sample and Hold Gates Using Field Effect Transistors", p. 49, lignes 18-46; Figure 1.
Funkschau, No. 4, Fevrier 1982, pp. 70-72, Munich, DE; W. Strossenreuther: "Nf-Strospannung wirksam unterdruckt", En entier.

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