Sampling and hold circuit

Details Sampling and hold circuit Sampling and hold circuit

2002-11-21

2004-03-02

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S096000

Reexamination Certificate

active

06700417

ABSTRACT:

This nonprovisional application claims priority under 35 U.S.C. §119(a) on Patent Application No. 2001-356081 filed in JAPAN on Nov. 21, 2002, which is herein incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a sampling and hold circuit that samples and holds a pair of input signals having mutually opposite voltage levels.
2. Description of the Related Art
A prior sampling and hold circuit is described in the following with reference to FIG.
7
. The sampling and hold circuit
100
in
FIG. 7
includes a differential amplifier circuit
101
, NMOS transistors Qa through Qf, and capacitors Ca and Cb. Clock signals CK
1
, CK
2
, and CK
2
B are respectively input to the gates of NMOS transistors Qb, Qc, and Qa from a clock-signal generator circuit (not illustrated). The clock signals CK
1
, CK
2
, and CK
2
B are also respectively input to the gates of NMOS transistors Qe, Qf, and Qd. The clock signal CK
2
B is a signal obtained by inverting the signal level of the clock signal CK
2
.
This sampling and hold circuit
100
has a positive-side input terminal
105
and a negative-side input terminal
106
. A positive-side analog signal is input to positive-side input terminal
105
, and a negative-side analog signal is input to negative-side input terminal
106
. The positive-side and negative-side analog signals are a pair of signals having mutually opposite signal levels. The sampling and hold circuit 100 samples, holds and then outputs the input analog signals based on the predetermined clock signals output from the clock-signal generator circuit.
When the sampling and hold circuit
100
performs sampling, NMOS transistors Qa, Qb, Qd, and Qe are turned on, and NMOS transistors Qc and Qf are turned off to thereby assume a cut-off state. In this way, the input voltage ViP of the positive-side analog signal input to positive-side input terminal
105
is sampled to capacitor Ca, and the input voltage ViM of the negative-side analog signal input to negative-side input terminal
106
is sampled to capacitor Cb.
Next, when holding is performed, NMOS transistors Qa, Qb, Qd, and Qe are turned off to assume the cut-off states, and NMOS transistors Qc and Qf are turned on to assume conductive states. In this way, the voltage sampled to capacitor Ca is held and input to one input terminal INP of differential amplifier circuit
101
, and output as a positive-side output voltage VoP from the output terminal
107
corresponding to input terminal INP. Similarly, the voltage sampled to capacitor Cb is held and input to the other input terminal INM of differential amplifier circuit
101
, and output as a negative-side output voltage VoM from the output terminal
108
corresponding to input terminal INM.
Here, we assume that the mutual conductance at input terminal INP of differential amplifier circuit
101
and the mutual conductance at input terminal INM of differential amplifier circuit
101
are the same gm.
FIG. 8
shows an equivalent circuit of sampling and hold circuit
100
during the sampling stage in this case. In
FIG. 8
, the equivalent resistance of NMOS transistor Qa while Qa is turned on is denoted by Ra, and the equivalent resistance of NMOS transistor Qd while Qd is turned on is denoted by Rd. In
FIG. 8
, when the frequency of the analog signals input to positive-side input terminal
105
and negative-side input terminal
106
becomes high, the impedances of capacitors Ca and Cb decline.
Therefore, the voltages VsP and VsM at the input terminals of differential amplifier circuit
101
are originally a virtual ground voltage, but there has been a problem that they greatly vary from the virtual ground voltage. Therefore, when such a sampling and hold circuit is used, for example, in an analog-to-digital (A-D) converter, if the frequency of the analog signals input to sampling and hold circuit
100
becomes equal to or greater than the Nyquist frequency, the voltages greatly vary from the virtual ground voltage. Therefore, there has been a problem that distortions occur by the influence of non-linearity of switches, amplifiers, and the like, so that the SNDR of the A-D converter deteriorates.
SUMMARY OF THE INVENTION
The present invention has been made to eliminate the above problems and has for Its object to obtain a sampling and hold circuit that can suppress voltage variation at the input terminals of a differential amplifier circuit that form virtual grounds, depending on the frequency of input analog signals.
To this end, a sampling and hold circuit according to the present invention samples and holds, at a predetermined timing, a pair of first and second input signals having opposite voltage levels. The sampling and hold circuit is equipped with a first circuit section having a first capacitor that samples and holds the first input signal and having a predetermined impedance and a second circuit section having a second capacitor that samples and holds the second input signal and having a predetermined impedance. The voltage held by the first capacitor in the first circuit section is input to a first input terminal of a differential amplifier circuit section, and the voltage held by the second capacitor in the second circuit section is input to a second input terminal of the differential amplifier section. The sampling and hold circuit is also equipped with a third circuit section having a third capacitor that has the same capacitance as that of the first capacitor, having the same impedance as that of the first circuit section during sampling operation, and inputting the second input signal to the first input terminal of the differential amplifier circuit. The sampling and hold circuit is also equipped with a fourth circuit section having a fourth capacitor that has the same capacitance as that of the second capacitor, having the same impedance as that of the second circuit section during sampling operation, and inputting the first input signal to the second input terminal of the differential amplifier circuit section.
In a preferred embodiment, the first circuit section comprises the first capacitor and a first transistor, and a predetermined voltage Vc
1
is always applied to a control-signal input terminal of the first transistor. The second circuit section includes the second capacitor and a second transistor, and a predetermined voltage Vc
2
is always applied to a control-signal input terminal of the second transistor. The third circuit section includes the third capacitor and a third transistor. The second input signal is input to the third capacitor, and the third transistor is turned on during sampling operation to input the second input signal to the first input terminal of the differential amplifier circuit section. The fourth circuit section comprises the fourth capacitor and a fourth transistor. The first input signal is input to the fourth capacitor, and the third transistor is turned on during sampling operation to input the first input signal to the second input terminal of the differential amplifier circuit section.
According to the sampling and hold circuit of the present invention, the influence of frequency variation in the first and second input signals and the like is canceled at the first and second input terminals of the differential amplifier circuit section, so that voltage variation at the first and second input terminals of the differential amplifier circuit section that form virtual grounds can be reduced. Therefore, when the sampling and hold circuit of the present invention is used in an A-D converter and the like, even if the frequency of analog signals becomes equal to or greater than the Nyquist frequency, the occurrence of distortions in output signals can be suppressed.
In this case, it is desirable that the predetermined voltage Vc
1
is applied to the first transistor so that its equivalent resistance can become the same as the equivalent resistance of the third transistor while the third transistor is turned on, and the predetermined voltage Vc
2
is applied to the second trans

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