Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2000-03-02
2003-12-30
Saras, Steven (Department: 2675)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S100000, C345S546000
Reexamination Certificate
active
06670942
ABSTRACT:
This application claims priority to European Patent Application No. 99200608.0 filed Oct. 29, 1999.
The invention relates to a method of converting a signal into a multiple signal, comprising the step of sampling and holding the signal in a plurality of sample & hold circuits of a stage.
The invention also relates to a sampler for converting a signal into a multiple signal, comprising an input circuit for receiving the signal, and at least one stage comprising a plurality of sample & hold circuits.
The invention further relates to a picture display device comprising a sampler as described above, and a picture display panel.
U.S. Pat. No. 5,654,735 describes a picture display device comprising such a sampler.
The patent describes a technique of driving a picture display panel in which a sampling method is used for driving a plurality of pixels simultaneously. Such a multipixel sampling method is particularly used in a liquid crystal display (LCD) with an active matrix. Such an LCD comprises pixel electrodes which are connected by means of switching elements to crossings of orthogonal data lines and scanning lines.
The sampler, corresponding to the video driver mentioned in said patent, delays the analog video signal for adapting the supply timing of the video signal to the picture display panel in conformity with the row intensity of the pixels. The video driver and the horizontal drive circuit of the picture display panel are driven by a timing circuit.
The video driver is illustrated as a first stage of three sample & hold (S&H) circuits and a second stage of another three S&H circuits. An S&H circuit of the first stage and an S&H circuit of the second stage connected thereto form part of a channel. Each channel is further provided with an amplifier. In this device, a video signal at the input is distributed across the three channels which thus jointly produce a threefold signal. The S&H circuits of the first stage are successively driven with separate signals so that each of them samples a successive part of the signal. This part is held and is available at the three outputs of the first stage which are connected to the three inputs of the second stage. The S&H circuits of the second stage are synchronously driven by a single signal. This means that they sample the signals, presented by the first stage, at the same instant. The parts of the signal are then simultaneously available at the output of this stage for a maximum period of three clock periods. The outputs of this stage are connected to three data lines of the picture display panel. The picture display panel is thus driven per block of three data lines and the clock frequency is reduced to one third.
The synchronous processing by the second stage must take place before the first S&H circuit of the first stage processes a successive part of the input signal. This means that the time for the second stage to sample the output signal of the last S&H circuit of the first stage, i.e. in the last channel, is short. Consequently, problems such as, for example, uniformity problems and ghost images, may occur when processing the signal.
It is an object of the invention to extend the sampling time of the signal.
To this end, the method according to the invention is characterized in that the signal is applied in the form of bursts to the stage, with successive bursts being separated by a time interval, A burst is a part of the signal which is transmitted at an increased clock frequency. After the last sample & hold circuit of the stage has sampled the signal, the signal is frozen during the time interval. After the time interval, the signal is sampled again by the first sample & hold circuit of the stage. The sampling time is extended by this method.
With this invention, an extra stage, which is added to prevent problems due to the short sampling time in the last channel, may be dispensed with in many cases.
As already mentioned the clock frequency of the signal must be increased, because the same information must be passed on (in the burst) within a shorter time.
In a first embodiment, the time interval is chosen to be approximately equal to the duration of a burst. This embodiment has the advantage that one stage yields approximately the same effect as two stages, as is known from said patent. The time interval is chosen, for example, to be such that the multiple signal satisfies the input specifications of a device connected to the output of the sampler.
A further embodiment provides a lower clock frequency than the first embodiment. This further embodiment is therefore characterized in that the time interval is chosen to be shorter than the duration of a burst. Here again, the stable time in the last channel after the first stage is extended and the risk of uniformity problems is reduced. In many cases, a subsequent stage will still be necessary to further extend the stable time. The time interval is chosen, for example, to be such that the multiple signal after the first stage can be satisfactorily sampled by the next stage. An extra stage, which would have been added to inhibit uniformity problems, can be dispensed with.
In a general embodiment, a sampler as described above is present in a picture display device comprising a picture display panel, wherein an output of the sampler is connected to the picture display panel. When used in such a picture display device, the invention ensures that the risk of uniformity problems and ghost images is reduced.
When using a burst input clock signal, a memory is required. For this purpose, the memory may be used which is generally already present in the picture display device for scaling and frame buffering.
According to the invention, the design of the sampler can be simplified so that a more compact design is possible at lower cost. A compact design is suitable for integration because the power consumption can be maintained small.
REFERENCES:
patent: 5113181 (1992-05-01), Inoue et al.
patent: 5557302 (1996-09-01), Levinthal et al.
patent: 5654735 (1997-08-01), Nakajima
patent: 5757351 (1998-05-01), Lin et al.
patent: 5973661 (1999-10-01), Kobayashi et al.
patent: 0760508 (1997-03-01), None
“Data Transfer Rate Reduction for Liquid Crystal Display Source Driver Integrated Circuit using Memory Block Addressing”, IBM Technical Disclosure Bulletin, vol. 40. No. 8, Aug. 1997.
Lammers Matheus J. G.
Van Asma Cornelis G. M.
Anyaso Uchendu O.
Gathman Laurie E.
Koninklijke Philips Electronics , N.V.
Saras Steven
LandOfFree
Sampler for a picture display device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Sampler for a picture display device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Sampler for a picture display device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3168539