Sampled current-integrating decision feedback equalizer and...

Pulse or digital communications – Equalizers – Automatic

Reexamination Certificate

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C375S229000, C375S230000, C375S232000

Reexamination Certificate

active

08085841

ABSTRACT:
A decision feedback equalizer (DFE) and method including a branch coupled to an input and including a sample-and-hold element configured to receive and sample a received input signal from the input and a current-integrating summer. The current-integrating summer is coupled to an output of the sample-and-hold element. The summer is configured to receive and sum currents representing at least one previous decision and an input sample. The at least one previous decision and the input sample are integrated onto a node, wherein the input sample is held constant during an integration period, thereby mitigating the effects of input transitions on an output of the summer.

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patent: 2006/0291552 (2006-12-01), Yeung et al.
patent: 2007/0147559 (2007-06-01), Lapointe
Emami-Neyestanak et al., A Low-Power Receiver with Switched-Capacitor Summation DFE; 2006 Symposium on VLSI Circuits Digest of Technical Papers; 2006; pp. 192-193.
Grozing et al., Sampling Receiver Equalizer with Bit-Rate Flexible Operation up to 10 Gbit/s; IEEE; 2006 pp. 51-519.
T. Beukema et al., A 6.4-Gb/s CMOS SerDes Core with Feed-Forward and Decision-Feedback Equalization, IEEE J. Solid-State Circuits, vol. 40, pp. 2633-2645, Dec. 2005.

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