Sampled amplitude read/write channel employing a sub-baud rate w

Details Sampled amplitude read/write channel employing a sub-baud rate w Sampled amplitude read/write channel employing a sub-baud rate w

1998-01-14

2000-02-22

Kim, W. Chris

Dynamic magnetic information storage or retrieval

General processing of a digital signal

Data clocking

G11B 509

Patent

active

060287284

ABSTRACT:
A sub-baud rate write circuit is disclosed which writes RLL encoded channel data to a disk storage medium using a write clock frequency significantly below the baud rate. This allows for a higher channel data rate without increasing the cost and complexity of the write circuitry. The write circuitry operates by re-encoding the RLL encoded channel data according to a particular mapping to generate write data at the write clock rate, and then writing the write data to the disk at appropriate phase delays. The phase delays are generated by passing the write clock through an array of delay circuits. The resulting write signal is the same as if the RLL encoded data were written to the disk using a baud rate write clock. The write circuitry of the present invention is ideally suited for use in a sub-sampled read/write channel where the object is to reduce the cost and complexity by clocking the entire channel at a frequency significantly below the baud rate.

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U.S. application No. 08/681,578, Reed et al., filed Jul. 29, 1996.
Jan W. M. Bergmans, "A Partial Response Decoding of Rate 1/2 Modulation Codes for Digital Storage" IEEE Transactions On Communications, vol. 39, No. 11, pp. 1569-1581, Nov. 1991.
Jan W. M. Bergmans, "A Partial Receiver For Miller-Squared Encoded Signals with Half the Usual Operating Speed", IEEE Transactions on Magnetics, vol. 26, No. 5, Sep. 1990.

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