Sampled amplitude read channel employing interpolated timing rec

Dynamic magnetic information storage or retrieval – General processing of a digital signal – Data clocking

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360 40, G11B 509

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057711275

ABSTRACT:
In a computer disk storage system for recording binary data, a sampled amplitude read channel comprises a sampling device for asynchronously sampling pulses in an analog read signal from a read head positioned over a disk storage medium, interpolated timing recovery for generating synchronous sample values, and a sequence detector for detecting the binary data from the synchronous sample values. The sequence detector comprises a demodulator for detecting a preliminary binary sequence which may contain bit errors, a remodulator for remodulating to estimated sample values, a means for generating sample error values, an error pattern detector for detecting the bit errors, an error detection validator, and an error corrector for correcting the bit errors. The remodulator comprises a partial erasure circuit which compensates for the non-linear reduction in amplitude of a primary pulse caused by secondary pulses located near the primary pulse. The error pattern detector comprises a peak error pattern detector and, if an error pattern is detected, a means for disabling the error pattern detector until the detected error pattern has been fully processed. The error detection validator checks the validity of a detected error event and, if valid, enables operation of the error corrector.

REFERENCES:
patent: 3648265 (1972-03-01), Kobayashi et al.
patent: 5521945 (1996-05-01), Knudson
patent: 5696639 (1997-12-01), Spurbeck et al.
Takushi Nishiya, PERD: Partial Error Response Detection, IEEE Inter Mag '95, San Antonio, Texas, Apr. 1995.
Takushi Nishiya and Hideyuki Yamakawa, "PERD: Partial Error Response Detetion", IEEE Transactions On Magnetics, vol. 31, No. 6, Nov. 1995.
Roger Wood, "Turbo-PRML: A Compromise EPRML Detector" IEEE Transactions On Magnetics, vol. 29, No. 6, Nov. 1993.
Hideyuki Yamakawa, "SPERD: Simplified Partial Error Response Detection", IEEE Inter Mag '95, San Antonio, Texas, Apr. 1995.
U.S. application No. 08/546,162, Spurbeck et al., filed Oct. 20, 1995.

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