Television – Format conversion
Reexamination Certificate
2000-03-27
2003-06-03
Hsia, Sherrie (Department: 2614)
Television
Format conversion
C348S663000, C348S625000
Reexamination Certificate
active
06573940
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to video processing, and more particularly to sample rate converters suitable for use with video and other types of data.
Sample rate converters are widely used in digital signal processing to convert data samples that have been sampled at one sample rate to data samples at a second sample rate. The second sample rate may be selected for ease of data processing, to synchronize the output data samples to a particular output clock, or for other purposes. For example, in video applications, the input video signal may be sampled at a fixed sample rate (e.g. 27.0 MHz) and sample rate conversion may be used to generate video samples at a second sample rate related to the color subcarrier frequency (e.g. 14.318 MHz for NTSC compliant video). Sample rate conversion is also commonly used for audio, digital demodulation, and other applications.
Various techniques are conventionally used for sample rate conversion. In one simple technique, the input samples are upconverted to a higher sample rate, filtered, and then decimated to the required output sample rate. This technique generally works well when the input and output sample rates are related by a ratio of integers. However, the filtering is performed at the high upconverted rate, and this is typically undesirable or may be impractical for some applications.
Sample rate conversion is also conventionally achieved through the use of an interpolator. For each output clock cycle, the interpolator computes an interpolated sample at a particular point in time (e.g. corresponding to the rising edge of the output clock). The interpolated sample is generated based on two or more input samples, and is used as an estimate for the desired output sample. The interpolator can be implemented using delay elements, multipliers, and an adder. However, implementation of multipliers in hardware or software is typically costly.
Thus, sample rate converters that provide the required functionality and can be efficiently implemented are highly desirable.
SUMMARY OF THE INVENTION
The invention provides sample rate converter architectures that can be more efficiently implemented than conventional ones. A sample rate converter receives input samples at an input sample rate f
IN
and generates output samples at an output sample rate f
OUT
. Sample rate conversion can be achieved using interpolation, wherein each output sample is computed as a sum of a number of weighted input samples. The scaling factors to generate the weighted input samples vary over time depending on the relative phase between the input and output sample clocks.
Simplification of the sample rate converter is first achieved by implementing the multipliers with scalers and adders. Further simplification is achieved by using a smaller number of adders, and providing the required operands to the adders via selector elements (e.g. multiplexers). The invention provides various arrangements for the adders and selector elements. The arrangement most suitable for a particular application is dependent on a number of factors, such as the number of taps for the interpolator being implemented, the number of phases to be interpolated, the resolution of the scaling factors, and others.
An embodiment of the invention provides a sample rate converter that includes a number of selector elements coupled to a summing circuit. Each selector element receives a respective set of one or more processed data samples and provides one of the processed data samples. Each processed data sample is generated by delaying an input sample by zero or more clock cycles and scaling the sample by a particular scaling factor (e.g. 2
N
, where N is 0, 1, 2, and so on). The summing circuit receives and combines the processed data samples from the selector elements to generate an output sample. The sample rate converter typically further includes a delay and scaler circuit that receives the input sample and provides one set of processed data samples for each selector element. The elements of the sample rate converter can be configured to implement a K-tap, P-phase interpolator, where K and P are each equal to two or greater, and P can further be a power of twos.
The delay and scaler circuit can include one or more delay elements coupled in series and to a scaling circuitry. One delay element receives the input sample, and each delay element provides a delayed sample. The scaling circuitry receives the input sample and one or more delayed samples, and scales selected ones of the input and delayed samples. The scaling can be implemented by simply bit-shifting the samples.
Another embodiment of the invention provides a sample rate converter that includes a delay circuit, a number of scaler and adder circuits, a number of selector elements, and a summing circuit. The delay circuit receives an input sample and provides a set of one or more delayed samples. The scaler and adder circuits couple to the delay circuit, and each scaler and adder circuit receives the input sample or one delayed sample and provides a respective set of processed samples. The selector elements couple to the scaler and adder circuits, and each selector element receives the respective set of processed data samples and provides one of the processed data samples. The summing circuit receives and combines the samples provided by the selector elements to generate an output sample.
Each scaler and adder circuit can include zero or more delay elements coupled in series and further to at least one adder. The delay elements delay respective received samples. The adder receives and combines selected ones of the received and delayed samples to generate the set of processed data samples.
Yet another embodiment of the invention provides a sample rate converter that includes a delay circuit, a number of scaler and adder circuits, and a selector element. The delay circuit receives an input sample and provides a set of one or more delayed samples. Each scaler and adder circuit receives a set of input and delayed samples and provides an interpolated sample. The selector element receives interpolated samples from the scaler and adder circuits and provides one of the interpolated samples as an output sample.
Another embodiment of the invention provides a method for performing sample rate conversion. In accordance with the method, a number of sets of processed data samples are received. Each processed data sample is generated by delaying an input sample by zero or more clock cycles and scaling the sample by a particular scaling factor. One processed data sample from each of the plurality of sets is selected. The selected processed data samples from the sets, which are associated with a particular phase to be interpolated, are combined to generate an output sample.
The invention further provides video decoders, other devices, and signal processing techniques that incorporate the sample rate converters described above.
The foregoing, together with other aspects of this invention, will become more apparent when referring to the following specification, claims, and accompanying drawings.
REFERENCES:
patent: 4819062 (1989-04-01), Dongil et al.
patent: 5889562 (1999-03-01), Pau
Dinh & Associates
Hsia Sherrie
Techwell, INC
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