Sample rate converter

Details Sample rate converter Sample rate converter

1999-06-02

2003-06-24

Pham, Chi (Department: 2631)

Pulse or digital communications

Apparatus convertible to analog

C341S061000

Reexamination Certificate

active

06584145

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to the field of digital signal processing in digital communication. More particularly, the invention relates to a resampling system used at the transceiver (transmitter and/or receiver) end of digital communication.
2. Description of Related Art
The telephone networks currently in place were originally designed for transmission of electrical signals carrying human speech. Since human speech is generally confined within a band ranging from 0 Hertz to 3,400 Hertz, telephone networks were designed to provide telephone lines to each user which were capable of handling frequencies within this range. Today, these same telephone lines, which connect a service user to a central office, are in place, permitting communication of only voice data or analog modem transmissions of not more than 56,000 bits per second. However, connections between central offices of telephone networks are provided by high-bandwidth fiber optic transmission facilities in nearly every telephone network worldwide.
Because the local telephone lines which connect an end user to a central office are only capable of handling frequencies of up to 3,400 Hertz, communication equipment utilizing these lines, such as dial modems or fax modems, have been accordingly limited in bandwidth. Despite the presence of high bandwidth fiber optic lines between central offices, users remain limited in the bandwidth available to them because the local lines serve as a bottleneck. New technologies, such as the Internet or video conferencing, demand that the bottleneck be removed.
Digital Subscriber Line (DSL) technologies are capable of removing the bottleneck. DSL permits a user to communicate over the existing telephone lines at a rate of tens of millions of bits per second. In order to utilize DSL, a site must be equipped with a transceiver (a DSL modem) which communicates, via the existing telephone lines, with another transceiver located at the central office of the network access provider, generally the local telephone company.
FIG. 1
shows one application of a digital communication system for implementing various DSL technologies, in which the first and second clocks are typically not synchronized. The digital communication system
10
comprises a transmitter
12
, a receiver
16
, and an analog channel
14
connecting the transmitter
12
to the receiver
16
. The transmitter comprises an encoder
18
which samples with a baud rate, BAUDFREQ, and other modules not shown. The receiver
16
comprises a sigma-delta modulated (SDM) analog-to-digital converter (ADC), a resampler
22
, and a clock recovery circuit
24
. The digital signals at the transmitter
12
is encoded and converted to analog signals which are transmitted to the receiver
16
via the analog channel
14
. At the receiver
16
, the analog signals are converted to digital signals via sampling at the ADC
20
and resampling at the resampler
22
. The resampled digital signals can be outputted to an end user. A clock recovery circuit can be included to adjust the phase of the clock used to resample a signal.
FIG. 2
shows a typical resampling receiver
25
, as would be used in communication system
10
of FIG.
1
. Receiver
25
comprises a sigma-delta modulated (SDM) ADC
26
, a resampler
28
coupled to the output of the ADC
26
, and a clock recovery circuit
29
. Clock recovery circuit receives the digital signal (data stream) outputted by resampler
28
and provides a phase shift value or a recovered clock to an input of resampler
28
. In alternative implementations, the clock can be generated by means other than recovery from the signal itself.
As shown in
FIG. 2
, the ADC
26
comprises a noise shaper
30
for shaping the analog input to the ADC
26
, an A/D converter
32
for converting the shaped analog input to one of N digital sample levels at each clock tick (a timing point such as a rising or falling edge) of an oversampling clock input to the ADC
26
, and a low-pass filter (LPF)
34
, which filters and decimates the digital sample stream. The resampler
28
comprises an upsampler
36
coupled to an input of resampler
28
(i.e. the digital signal from the ADC
26
), a LPF
38
coupled to the output of the upsampler
36
, and a sample selector
40
coupled to an output of LPF
38
. In alternative embodiments, LPF
38
can be an interpolator. Accordingly, the receiver
25
transforms an analog, time-continuous signal into a stream of digital samples representing the value of the analog signal at clock ticks of clocks H, H/D, HU/D, and L′. The input analog signal is first digitized at one clock rate, H, downsampled to another clock rate of H/D, upsampled to yet another clock rate UH/D, and then resampled to a clock rate L′. Thus, the digital signal, from the ADC
26
and the resampler
28
, is downsampled, filtered, upsampled, and re-filtered. All of these transformations result in loss of accuracy and consume unnecessary signal processing resources.
Accordingly, there is a need for an improved means for resampling sampled signals at an arbitrary phase.
U.S. Pat. No. 5,513,209 discloses a digital resampling system which includes a non-decimating filter, a phase indicator, a sample selector, a weight generator, a weighed averager, and an output clock. However, in the '209 patent, a phase offset (i.e. the phase difference between ticks of clocks) calculated from the phase indicator is not very accurate because the unit of measurement of the phase offset is the number of clock cycles of one of the two clocks. Further, the phase calculating circuit require two clock inputs, i.e. CLK
1
and CLK
2
. Furthermore, the resampling system of the '209 patent requires significant modifications be made in a typical receiver. For example, the '209 patent requires a non-decimating low pass filter (LPF) to be used instead of an upsampler and a decimating LPF which are used in a typical receiver.
Therefore, there is a need for an improved resampling system for converting a first digital signal to a second digital signal with a more accurate phase offset.
It can also be seen that there is a need for an improved resampling system without requiring significant modifications of a typical receiver.
SUMMARY OF THE INVENTION
To overcome the limitations in the prior art described above, and to overcome other limitations that will become apparent upon reading and understanding the present specification, the present invention discloses an apparatus for recovering timing of a digital signal for a transceiver.
The present invention discloses an apparatus for performing a sample rate conversion from a first digital signal to a second digital signal where both represent the same data but sampled at different clock rates.
The present invention solves the above-described problems by providing a resampling system, e.g. a sample rate converter, which uses a numerical controlled oscillator (NCO) to determine a phase relation between the digital signals and to control an interpolation/decimation filter of the sample rate converter.
In one embodiment of the present invention, a converter for converting a first digital signal representing an analog signal into a second digital signal representing the analog signal, comprises: a converter filter, the converter filter receiving the first digital signal which is sampled at a first clock and outputting the second digital signal sampled at a second clock, the converter filter receiving a phase control signal which controls conversion from the first digital signal to the second digital signal; and a timer, the timer receiving the second clock and a baud rate of the analog signal and generating the first clock and the phase control signal for the converter filter.
Other embodiments of the converter in accordance with the principles of the invention may include alternative or optional additional aspects. One such aspect of the present invention is that the timer includes: an accumulator which accumulates the baud rate at each tick o

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