Sample-hold circuit with outputs taken between gates of dynamic

Details Sample-hold circuit with outputs taken between gates of dynamic Sample-hold circuit with outputs taken between gates of dynamic

1989-07-06

1991-05-14

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Shift register

Compensating for or preventing signal deterioration

377 76, 377 77, 377 79, 365240, H03K 2140, H03K 2112, H03K 2344, G11C 11407

Patent

active

050162632

ABSTRACT:
A sample-hold circuit comprises a large number of sample-hold elements, and a multi-stage shift register for controlling sampling timings of the sample-hold elments, including a large number of stages corresponding to respective sample-hold elements, wherein each of stages of the multi-stage shift register includes an input gate for taking a signal shifted from the preceding stage thereinto, an output gate for shifting the signal taken in by the input gate to the succeeding stage, respective sampling timings of the sample-hold elements corresponding to respective stages being determined by signals taken in between the input and output gates through the input gates at the respective stages. Waveforms of output signals from respective stages for determining the sampling timing are not affected by interstage wiring capacity. Accordingly, where a multi-stage shfit register is made up as a folded array, unevenness occurs in the interstage wiring capacity, but such an unevenness has no bad influence on the sampling timing.

REFERENCES:
patent: 3657699 (1972-04-01), Rocher et al.
patent: 3665496 (1972-05-01), Donjon
patent: 4152606 (1979-05-01), Hornak
patent: 4295055 (1981-10-01), Takemoto et al.
patent: 4802136 (1989-01-01), Nose et al.
patent: 4873671 (1989-10-01), Kowshik et al.
Hodges et al., "Potential of MOS Technologies for Analog Integrated Circuits", IEEE Journal of Solid-State Circuits, vol. SC-13, No. 3, Jun. 1978, pp. 285-294.

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