Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
1999-10-06
2001-05-15
Nuton, My-Trang (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
Reexamination Certificate
active
06232804
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a sample hold circuit incorporating a switch of a low distortion capable of reducing a distortion of an output signal by changing an ON resistance of the switch to which an analogue input signal is supplied.
2. Description of the Related Art
FIG. 1
is a circuit diagram showing a configuration of a conventional sample hold circuit. In
FIG. 1
, the reference number
121
designates a MOS transistor switch, and
122
denotes a sample hold processing section. Thus, the conventional sample hold circuit comprises the MOS transistor
121
for sampling an analogue input signal and the sample processing section
122
for sampling the analogue input signal.
Next, a description will be given of the operation of the conventional sample hold circuit shown in GIG.
1
.
When the conventional sample hold circuit performs sampling of analogue input signals, the ON resistance R of the MOS transistor switch
121
is proportional to the inverted value of a value obtained by subtracting a voltage difference V
GS
between a gate terminal G and the source terminal S of the MOS transistor switch
121
from a value of a threshold voltage V
th
of the MOS transistor switch
121
. For example, the ON resistance can be expressed by the following equation (1):
R
=1/&bgr;(
V
GS
−V
th
) (1)
where &bgr;=&mgr;
0
W/L, &mgr;
0
is a gain coefficient, W is a channel width, and L is a channel length.
Accordingly, when the conventional sample hold circuit shown in
FIG. 1
samples the analogue input signal through the MOS transistor switch
121
, the ON resistance value R of the switch is changed according to the voltage of the analogue input signal. Thereby, the output signal held by and output from the MOS transistor switch
121
includes a signal distortion. This signal distortion generated in the conventional sample hold circuit shown in
FIG. 1
introduces a drawback that a signal to noise ratio (S/N ratio) is decreased. The S/N ratio is used as an index of the performance of the A/D converter.
In order to eliminate the signal distortion in the output wave from the MOS transistor switch
121
in the conventional sample hold circuit, the following methods are used.
In a first method, a voltage amplitude Vdd of the clock signal CLK to be supplied to the gate terminal G of the MOS transistor switch
121
is set to a large value. Thereby, the dependency of the ON resistance R of the MOS transistor switch
121
on the input voltage of the analogue input signal is proportional to the inverted value of the voltage amplitude squared VDD
2
of the clock signal CLK. This conventional method can decrease the signal distortion of the output wave of the sample hold circuit.
In a second method, a circuit to overlap the input signal to the clock signal CLK to be supplied to the gate terminal G of the MOS transistor switch
121
is introduced so that a voltage difference between the gate terminal G and the source terminal S of the MOS transistor switch
121
becomes a constant value.
In a third method, a size of the MOS transistor switch
121
is increased. This method means that the value &bgr; in the above equation (1) is increased. Because the dependency of the ON resistance T of the MOS transistor switch on the input voltage of the analogue input signal is inversely proportional to the value &bgr;, the distortion of the output signal is decreased.
In a fourth method, a value V
th
of the threshold voltage of the MOS transistor switch is decreased.
In conventional sample hold circuits, one of the above methods, or a combination of the above first to fourth methods are used in order to decrease the distortion of the output wave from the MOS transistor switch incorporated in the sample hold circuit.
Because the conventional sample hold circuit has the above configuration, according to the recent improvements of MOS transistors in size, integration, and performance, it is required to use the voltage of 3 V in 0.5 &mgr;m process in order to keep a withstanding voltage at a gate terminal, the voltage of approximately 3V in 0.35 &mgr;m process, and the voltage of 2V or less in 0.2 &mgr;m process. This means the voltage of the power source tends to shift a lower voltage. In this case, the distortion of the output signal generated by the ON resistance of the MOS transistor switch in the sample hold circuit becomes a large factor. Thereby, the distortion of the output signal greatly limits an allowed range of the input voltage in the A/D converter. In the tendency toward a low voltage of the power source, the conventional first and second methods described above can not eliminate the adverse effect by the distortion of the output wave from the MOS transistor switch in the sample hold circuit while keeping the withstanding voltage at the gate terminal. In addition, in the low voltage of the power source, the third and fourth conventional methods described above can not eliminate completely the adverse effect by the distortion of the output wave from the MOS transistor switch in the conventional sample hold circuit when this MOS transistor switch enters ON.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is, with due consideration to the drawbacks of the conventional technique, to provide a sample hold circuit using a switch capable of decreasing the adverse effect by the distortion of the output wave of the sample hold circuit even if a power source of a low voltage is used.
In accordance with a preferred embodiment of the present invention, a sample hold circuit comprises an input voltage decision section for comparing an analogue input signal with each reference signal having a predetermined voltage, an analogue switch section of a low distortion having a switch of a constant resistance value for processing so that an ON resistance of the analogue switch section for inputting the analogue input signal has a constant value in spite of a level of an input voltage of the analogue input signal according to a decision result from the input voltage decision section, and a sample hold processing section for sampling the analogue input signal from the analogue switch section of a low distortion.
In the sample hold circuit as another preferred embodiment according to the present invention, the input voltage decision section comprises a reference voltage system comprising a plurality of means for generating and supplying a plurality of reference voltages each having a predetermined voltage, a comparison block comprising a plurality of comparison circuits, corresponding to the plurality of reference voltages, for comparing the analogue input signal with the plurality of reference voltages, and a switch off block comprising a plurality of blocks corresponding to the plurality of reference voltages. In the sample hold circuit, the switch of a constant resistance value comprising a base switch and a plurality of unit switches corresponding to the plurality of comparison circuits, and each of the plurality of reference voltages is weighted, the plurality of comparison circuits compare the input voltage the analogue input signal with the plurality of reference voltages when the switch of a constant resistance value enters ON, and the plurality of unit switches are selectively activated by supplying output signals, obtained by logical AND operation between the comparison results from the plurality of comparison circuits and a clock signal to be supplied to the analogue switch of a low distortion, to a gate terminal of each unit switch so that a synthetic ON resistance of an ON resistance of the base switch and ON resistances of the plurality of unit switches becomes a constant value according to the input voltage of the analogue input signal.
In the sample hold circuit as another preferred embodiment according to the present invention, each of the plurality of blocks forming the switch off block comprises a selection circuit made up of a MOS transistor, and an ON/OFF operation of each unit switch forming
Ito Masao
Kumamoto Toshio
Shigenobu Takeshi
Burns Doane , Swecker, Mathis LLP
Mitsubishi Denki & Kabushiki Kaisha
Nuton My-Trang
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