Coded data generation or conversion – Converter calibration or testing
Reexamination Certificate
2009-05-06
2010-11-16
Jeanglaude, Jean B (Department: 2819)
Coded data generation or conversion
Converter calibration or testing
C341S155000, C341S122000, C327S096000, C327S094000
Reexamination Certificate
active
07834786
ABSTRACT:
A sample hold circuit is provided for use in a time-interleaved A/D converter apparatus including a plurality of low-speed pipeline A/D converters which are parallelized. The sample hold circuit includes a sampling capacitor and a sample hold amplifier, and operates to sample and hold an input signal by using a switched capacitor. An adder circuit of the sample hold circuit adds a ramp calibration signal to the input signal, by inputting the ramp calibration signal generated to have a frequency identical to that of a sampling clock signal and a predetermined slope based on the sampling clock signal, into a sample hold amplifier via a calibration capacitor having a capacitance smaller than that of the sampling capacitor.
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Kawahito Shoji
Kurauchi Akira
Liu Zheng
Mashiko Koichiro
Shimizu Yasuhide
Jeanglaude Jean B
Semiconductor Technology Academic Research Center
Wenderoth , Lind & Ponack, L.L.P.
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