Computer graphics processing and selective visual display system – Display driving control circuitry – Physically integral with display elements
Reexamination Certificate
1998-06-16
2002-10-22
Hjerpe, Richard (Department: 2674)
Computer graphics processing and selective visual display system
Display driving control circuitry
Physically integral with display elements
C345S204000, C345S212000, C345S213000
Reexamination Certificate
active
06469699
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a sample and hold circuit for sample-holding a video signal based on a master clock, and more particularly to a sample and hold circuit to use suitably for a horizontal driving system of a liquid crystal display device.
2. Description of Related Art
Some liquid crystal display (LCD) devices have the structure in which a video signal is simultaneously inputted using multi-channels in order to reduce driving frequency of an LCD panel. In a horizontal driving system of liquid crystal display devices of this sort, a sample hold circuit for sampling simultaneously multi-bits (pixels) corresponding to the number of channels is used in order to input a video signal using multi-channels.
A conventional example of a sample and hold circuit used for a horizontal driving system of a liquid crystal display device of 6-dot simultaneous sampling is shown in FIG.
5
. In this drawing, the sample and hold circuit
100
comprises a inversion amplifier
101
for inverting an input video signal, six sample hold units (SH
1
to SH
6
)
102
to
107
corresponding to 6 channels which receive an output signal from the inversion amplifier
101
, and SHP generation circuit
108
for generating
6
types of sample hold pulses SHP
1
to SHP
6
corresponding to six sample hold units
102
to
107
based on a master clock MCLK given from the outside, and the sample and hold circuit
100
is IC (Integrated Circuit) structured.
A PLL (Phase-Locked Loop) circuit
110
for supplying a master clock MCLK is provided to the sample and hold circuit
100
as an external circuit. The PLL circuit
110
generates a master clock MCLK synchronously to a horizontal sync signal HSYNC namely a comparison reference signal. For 6-dot simultaneous sampling, the master clock MCLK is oscillated at a frequency 12 times that of the horizontal clock HCK which is used as a reference of horizontal scanning of the LCD.
Because, for example, the conventional sample and hold circuit used for a horizontal driving system of a 6-dot simultaneous sampling liquid crystal display device has the structure in which the master clock MCLK is transmitted from a PLL circuit
110
provided as a separate external circuit to the sample and hold circuit, the structure is inevitably provided with wiring for transmitting the master clock MCLK to an external substrate, and in an exemplary 6-dot simultaneous sampling, because frequency of the master clock MCLK is 12 times that of the horizontal clock HCK, the high frequency causes a problem of unwanted radiation. To reduce the unwanted radiation, additional parts dedicated for reduction of the unwanted radiation are required, and the number of parts of the circuit increases resulting in increased cost.
The present invention is accomplished in view of the above-mentioned problem, it is the object of the present invention to provide a sample and hold circuit with reduced unwanted radiation which does not require complex wiring for transmitting the master clock MCLK.
SUMMARY OF THE INVENTION
A sample and hold circuit in accordance with the present invention is a sample and hold circuit for sample-holding a video signal based on a master clock, and has the structure having a PLL circuit for generating a master clock synchronously to a comparison reference signal supplied from the external provided on the common substrate.
In the sample and hold circuit having the above-mentioned structure, the structure that the PLL circuit is provided on the common substrate and contained in the common IC allows the complex wiring to the external substrate for transmitting the master clock generated by the PLL circuit to be eliminated. Unwanted radiation due to complex wiring is reduced and need for parts to prevent unwanted radiation is eliminated in spite of high frequency of the master clock.
REFERENCES:
patent: 5369417 (1994-11-01), Tanaka
patent: 5602561 (1997-02-01), Kawaguchi et al.
patent: 5680149 (1997-10-01), Koyama et al.
patent: 5745093 (1998-04-01), Tsuzuki et al.
patent: 5874934 (1999-02-01), Ito
patent: 6011534 (2000-01-01), Tanaka et al.
patent: 6049318 (2000-04-01), Ota
patent: 6144355 (2000-11-01), Murata et al.
Hjerpe Richard
Maioli Jay H.
Sony Corporation
Tran Henry N.
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