Sample and hold phase detector having low spurious...

Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – Frequency of cyclic current or voltage

Reexamination Certificate

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Details

C327S009000

Reexamination Certificate

active

06525521

ABSTRACT:

TECHNICAL FIELD
This invention relates in general to the field of phase detectors and more specifically to a sample and hold phase detector with low spurious performance and method.
BACKGROUND
The design of sample and hold phase detectors for high-performance frequency synthesizers is a key for low spurious (reference feedthrough) frequency synthesizer designs. In
FIG. 1
there is shown a typical phase lock loop (PLL)
100
using a SH phase detector
102
. If the SH phase detector
102
is not perfect then spurs will show up in the output signal (f
out
)
104
. The offset frequencies of these spurs are multiples of the reference frequency (F
R
)
106
.
A simplified electrical model schematic of a prior art SH phase detector
200
using the PLL of
FIG. 1
is shown in FIG.
2
. While in
FIG. 3
, the waveforms for V
R
, V
SH
and V
PR
are shown. The V
R
signal is the ramp control voltage, the V
SH
signal is the sample and hold pulse, and the V
PR
signal is the pre-charge signal. It should be noted that the conventional digital block, which generates these signals, is not shown in FIG.
2
. SH phase detector
200
includes a ramp current generator
204
, a ramp capacitor, C
R
206
, a sample and hold switch
208
, a sample and hold capacitor, C
SH
210
and buffer
212
.
If the SH phase detector
200
is implemented in complimentary metal-oxide semiconductor (CMOS) using a deep sub-micron CMOS process as an example, the SH phase detector
200
will leak a current during the hold period. Line
302
in
FIG. 3
shows an ideal constant voltage level at node N
202
while the SH phase detector
200
is in the hold or locked condition. However, line
304
shows the actual voltage level at node N
202
due to leakage current. This leakage current causes a voltage drift which causes unwanted spurs to be generated by the synthesizer that uses the SH phase detector
200
. The leakage current can be large, typically in the order of one nano-amp if the SH switch
208
has low threshold voltage (V
T
) devices operating at high temperature.
In
FIG. 4
, there is shown a typical prior art CMOS switch implementation. For the example shown in
FIG. 4
, the leakage current (I
Leak
) will happen during the phase detector hold period
306
. The PMOS device
402
has a V
GS
=0 and an |V
DS
|=V
CC
−V
N
.
Since a typical prior art SH phase detector has a typically long hold period, for example, for a 200 KHz compare frequency [R, V signals], t
hold
is approximately 5 microseconds using a capacitor (C
SH
)=5 pF. The &Dgr;V
308
due to leakage is equal to: &Dgr;V=[I/C]×[t]=(1 nA/5 pF)×(5 uS)=1 millivolt. This &Dgr;V during lock can cause spurs at f
out
+/−200 kHz as large as −20 dBc (without the filter attenuation). The NMOS device
402
shown in
FIG. 4
will not suffer because it's V
GS
is −V
N
and the leakage current is too low. The leakage current
404
problem can be much more sever than other issues associated with SH phase detectors including clock feedthrough and charge injection due to the CMOS switch.
Conventional sample and hold (SH) phase detectors used in frequency synthesizers sometimes also suffer from voltage glitches during lock. One reason for this problem is the leakage current of the sampling switch which results in charge leakage in the holding capacitor. A need exists in the art for method of reducing the leakage current in a SH phase detector and hence improves the reference feedthrough issue in the frequency synthesizer using the SH phase detector.


REFERENCES:
patent: 3641258 (1972-02-01), Steckler
patent: 3992660 (1976-11-01), Kawashima et al.
patent: 4216396 (1980-08-01), Balaban et al.
patent: 4361769 (1982-11-01), Hatchett et al.
patent: 4810904 (1989-03-01), Crawford
patent: 5057793 (1991-10-01), Cowley et al.
patent: 5483154 (1996-01-01), Chen
patent: 5483687 (1996-01-01), Barrett et al.
patent: 5838180 (1998-11-01), Partyka

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