Sample and hold droop compensation circuit

Details Sample and hold droop compensation circuit Sample and hold droop compensation circuit

1983-09-29

1985-10-08

Zazworsky, John

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307310, 328151, G11C 2702

Patent

active

045462704

ABSTRACT:
A circuit for use in association with a sample and hold circuit for preventing a sampled signal voltage from changing with time. The storage capacitor port at the sample and hold circuit is connected through a resistor to a variable voltage divider so that by adjusting the tap of the divider the current through the resistor can be adjusted to match the bias current generated at the capacitor port by the sample and hold circuit. A temperature sensitive device is included in the voltage divider for varying tap voltage and, hence, the matching current with ambient temperature to compensate for corresponding changes in bias current. The voltage divider is connected between the sample and hold output and a common return path to ensure that the voltage at the tap is a function of the sampled voltage and the temperature only.

REFERENCES:
patent: 3480795 (1969-11-01), Benson et al.
patent: 3516002 (1970-06-01), Hillis
patent: 4352070 (1982-09-01), Beauducel et al.

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