Sample-and-hold digital phase-locked loop for ask signals

Details Sample-and-hold digital phase-locked loop for ask signals Sample-and-hold digital phase-locked loop for ask signals

1989-08-08

1990-08-07

Olms, Douglas W.

Pulse or digital communications

Repeaters

Testing

329347, 128419R, H03D 100

Patent

active

049474073

ABSTRACT:
A digital phase-locked looped generates a clock signal synchronized with a carrier signal modulated by amplitude shift keying (ASK). During periods when no carrier signal is present, the generated clock signal coasts at the frequency of the carrier signal most recently present, rather than trying to phase-lock on noise. A binary controlled digital oscillator generates the clock signal. A phase detector determines the difference between the phase of the carrier signal, when present, and the local clock signal. When the average amplitude of the carrier signal exceeds a prescribed threshold level, the phase detector output is sampled and passed to an integrator circuit, where the phase difference is integrated. The output of the integrator circuit is applied to a pulse generator, causing the pulse generator's duty cycle to change proportionally. In turn, the pulses are applied to the binary controlled digital oscillator, causing the frequency of the local clock signal to shift in a direction that minimizes the phase error between the local clock signal and the carrier signal. When the average amplitude of the carrier signal is less than the prescribed threshold level, the phase detector output is not smapled. In such case, the output of the integrator circuit remains at the value obtained from the most recent prior phase detector sample.

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patent: 4805189 (1989-02-01), Mahony
Holmes, J. K. et al., "A Second Order All-Digital Phase-Locked Loop," IEEE Transactions on Communications (Jan. 1974), pp. 62-68.
"Types SN54LS297, SN74LS297 Digital Phase-Locked Loop Filters," Texas Instruments Digital IC Handbook, (Jan. 1981), pp. 38-42.

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