Sample and hold circuits and methods

Details Sample and hold circuits and methods Sample and hold circuits and methods

2000-04-27

2001-12-11

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S091000, C327S534000, C327S538000

Reexamination Certificate

active

06329848

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of sample and hold circuits.
2. Prior Art
Sample and hold circuits are well known in the prior art, being commonly used to periodically sample analog signals and hold such sample for further processing, such as the conversion of the analog sample to a digital signal. In a typical sample and hold circuit, a capacitor is first coupled to the signal to be sampled for charging to the present value of the signal, after which the capacitor is disconnected from the signal to hold the signal voltage that existed at the time of disconnection. Typical systems using sample and hold circuits are clocked systems operating at relatively high frequency on rapidly changing input signals, requiring the rapid and accurate charging of the holding capacitor while also providing a sufficiently large capacitance for adequate holding of that signal after the capacitor is disconnected from the signal being sampled.
In the prior art, CMOS transmission gates have been commonly used as a sample switch to connect and disconnect the signals being sampled to and from the sample capacitor. Such transmission gates comprise a p-channel transistor and an n-channel transistor connected in parallel so that conduction will occur through the parallel combination when either or both transistors are turned on. The gates of the transistors in turn are driven by a common signal, with one of the gates being driven through an inverter so that the common signal will drive the gates to opposite rails to tend to turn on and turn off the two transistors in unison.
Such transmission gates are simple and work well in many application. However, they have certain characteristics that limit their performance, particularly in high speed applications. For instance, when the signal being sampled is approximately midway between ground and the power supply rail, both the n-channel and the p-channel devices will be conducting. As the input increases, however, the gate-source voltage of the n-channel device reduces, tending to turn the n-channel device off, whereas the gate-source voltage of the p-channel device increases, tending to turn the p-channel device on harder. Similarly, if the input signal is below the midway point, the n-channel device will turn on harder and the p-channel device will conduct less. Since these effects are not linear, the overall resistance of the parallel combination of the two devices is a nonlinear function of the signal being sampled. Also, the source-body and the drain-body junction capacitances are non-linear, further affecting the accuracy of the resulting sample voltage. Also, the parasitic channel to gate capacitance changes with input signal, increasing or decreasing the charging current flowing through the input resistor network to the channel capacitances. The net effect of these factors is a distortion in the sample voltage verses input voltage, which distortion increases as the source impedance of the input signal increases.
BRIEF SUMMARY OF THE INVENTION
Sample and hold circuits and methods to reduce distortion are disclosed. A signal to be sampled is connected across a capacitor through a field effect device, which field effect device is turned off when the sample voltage across the capacitor is to be held. When the field effect device coupling the sample voltage to the capacitor is turned on, the body and gate voltages of the field effect device are made to have a fixed voltage relative to the voltage being sampled, so that the characteristics of the field effect device are unaffected by signal variations during sampling or between samples. Exemplary embodiments are disclosed.


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