Sample-and-hold circuit with reduced clock feedthrough

Details Sample-and-hold circuit with reduced clock feedthrough Sample-and-hold circuit with reduced clock feedthrough

1995-11-06

1996-10-29

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

327 95, 327 96, 327337, 327 67, G11C 2702

Patent

active

055700489

ABSTRACT:
A sample-and-hold circuit comprises a first buffer stage, a first sampling switch, a sampling capacitor, and a feedback output amplifier for supplying a sampled output signal (Uout). The sampling capacitor is connected to an output of a second buffer stage, which has an input connected to earth. The output amplifier receives feedback via a third buffer stage and a second sampling switch and via a fourth buffer stage and a second sampling capacitor, which together with the first sampling switch are controlled by the same clock signal. The first sampling switch gives rise to clock feedthrough at the non-inverting input of the output amplifier. This clock feedthrough is cancelled by an equal clock feedthrough at the inverting input, so that the sampled output signal is freed from undesired clock feedthrough.

REFERENCES:
patent: 3555298 (1971-01-01), Neelands
patent: 4125813 (1978-11-01), Cubbison, Jr.
patent: 4199697 (1980-04-01), Edwards
patent: 4308468 (1981-12-01), Olson
patent: 4352070 (1982-09-01), Beauducel et al.
patent: 4517518 (1985-05-01), Ishigaki
patent: 4520283 (1985-05-01), Sasaki et al.
patent: 5162670 (1992-11-01), Itakura et al.
patent: 5216375 (1993-05-01), Tanigawa et al.
patent: 5258664 (1993-11-01), White

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