Sample and hold circuit with full signal modulation compensation

Details Sample and hold circuit with full signal modulation compensation Sample and hold circuit with full signal modulation compensation

1992-04-17

1994-05-17

Sikes, William L.

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307257, 307494, 307578, H03K 524

Patent

active

053131134

ABSTRACT:
A diode bridge (12) includes a plurality of diodes (D1,D2,D3,D4) for coupling an input voltage signal (Vin) through a resistor (RH) to a holding capacitor (CH) for sampling when the diodes (D1,D2,D3,D4) are forward biased, and uncoupling the voltage signal (Vin) from the capacitor (CH) for holding when the diodes (D1,D2,D3,D4) are reverse biased. A constant current drain (S1) causes a constant bias current (IBIAS) to flow out of the bridge (12) through first and second bias current nodes (N1,N2) to a voltage source (VEE). The nodes (N1,N2) are also connected through current source resistors (R1,R2) to a voltage source (VCC). A first current regulator (72) is bootstrapped to the input signal (Vin) and regulates first and second bias currents flowing into the nodes (N1,N2) to constant values (IBIAS/2) to compensate for resistive current source modulation. A second current regulator (92) is also bootstrapped to the input signal (Vin) and regulates bias current flowing through the resistor (RH) into the junction (20) between the resistor (RH) and the capacitor (CH) to a constant value (IBIAS/4) to compensate for output slew current modulation.

REFERENCES:
patent: 3179817 (1965-04-01), Bounsall
patent: 3721829 (1973-03-01), Benson
patent: 4518921 (1985-05-01), Logan
patent: 4540902 (1985-09-01), Ishikawa
patent: 4659945 (1987-04-01), Metz
patent: 4879478 (1989-11-01), Gershon
patent: 5124576 (1992-06-01), Jensen

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