Sample and hold circuit, multiplying D/A converter having...

Details Sample and hold circuit, multiplying D/A converter having... Sample and hold circuit, multiplying D/A converter having...

2008-12-23

2010-06-29

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Sample and hold

C341S172000, C341S155000

Reexamination Certificate

active

07746254

ABSTRACT:
A sample and hold circuit includes an op-amp, inverting-side capacitors, and non-inverting-side capacitors paired with the inverting-side capacitors. At least one capacitor pair serves as a feedback capacitor in a holding phase. A total capacitance of the inverting-side capacitors to which an input voltage is applied in a sampling phase is α, a total capacitance of the non-inverting-side capacitors to which the input voltage is applied in the sampling phase is β, a total capacitance of the inverting-side capacitors to which the input voltage is applied in a holding phase is γ, and a total capacitance of the non-inverting-side capacitors to which the input voltage is applied in the holding phase is η. α is substantially different from β. A total capacitance of a feedback capacitor pair is substantially equal to (α−β−γ+η)·(N/2), where N is a positive number.

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