Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Utility Patent
1998-12-10
2001-01-02
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S095000
Utility Patent
active
06169427
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to sample and hold circuits and, in particular, to sample and hold circuits which convert a single-ended input to a differential output.
DESCRIPTION OF RELATED ART
In many signal processing applications, an analog signal is produced which is to be further processed by, for example, converting the signal to a digital form. Many such analog signals are originally produced as a single-ended signal which is referenced to a circuit common. Single-ended signals are typically processed using circuitry which is asymmetric with respect to the circuit common. It is well known that a differential signal, a signal which represents the instantaneous, algebraic difference between two signals, both of which are referenced to a circuit common, provides several advantages over single-ended signals. One such advantage is improved immunity to noise where the noise is added equally to both components of the differential signal. Since differential signals are usually processed using balanced circuitry which responds to differences between inputs and which suppresses common mode signals such as noise present on both components, improved immunity to noise is achieved.
There is a need for circuitry which is capable of converting a single-ended analog signal to a differential signal. Such circuitry should be capable of operating at relatively high frequencies and should be capable of implementation in integrated circuit form, including CMOS implementations. Further, in order to enhance the operating speed it is preferably that such circuitry be capable of simultaneously sampling a new single-ended analog input while holding a differential signal output produced from an previous analog input so that the differential signal output can be processed by additional circuitry.
There exists prior art circuitry which is capable of providing some of the advantages of single-ended to differential conversions noted above, but not all of such advantages. As will become apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention together with the drawings, unlike the prior art, the subject invention is capable of providing all of these and other advantages.
SUMMARY OF THE INVENTION
A sample and hold circuit having a single-ended input and a differential output is disclosed. The circuit includes a differential amplifier having first and second inputs and first and second outputs, with the first and second outputs functioning as the differential output. First and second input capacitors are provided together with third, fourth, fifth and sixth feedback capacitors.
Switching circuitry is provided which is configured to switch between a sample mode and a hold mode. When in the sample mode, the switching circuitry operates to couple a first side of the first capacitor to the input, to couple a first side of the second capacitor to a first reference voltage, to couple second sides of the first and second capacitors together. In addition, the switching circuitry, when in the sample mode, is operable to couple first and second sides of the third capacitor to the first input and first output of the differential amplifier, respectively, to couple first and second sides of the fourth capacitor to the second input and second output, respectively, of the differential amplifier, to couple a first side of the fifth capacitor and a first side of the sixth capacitor to the first and second inputs of the differential amplifier, respectively, and the second sides of the fifth and sixth capacitors to second and third reference voltages, respectively.
When in the hold mode, the switching circuitry is operable to couple the first sides of the first and second capacitors together, to couple the second sides of the first and second capacitors to the first and second inputs of the differential amplifier, respectively, to couple the first sides of the fifth and sixth capacitors to the first and second inputs of the differential amplifier, respectively, and to couple the second sides of the fifth and sixth capacitors to the first and second outputs of the differential amplifier, respectively.
One aspect of this arrangement is that the differential output which corresponds to the input can be stored on the fifth and sixth feedback capacitors in the hold mode and the same input can then held on the third and fourth capacitors in the subsequent sample mode. This permits the output of the sample and hold circuit to be used during both the hold and the subsequent sample modes.
REFERENCES:
patent: 4988900 (1991-01-01), Fensch
patent: 5963156 (1999-10-01), Lewicki et al.
B. Rothenberg, et al., “A 20-Msample/s switched-capacitor finite-impulse response filter using a transposed structure”, IEEE J. Solid-State Circuits, pp. 1350-1356, (Dec. 1995).
G. Nicollini, et al., “A fully differential sample-and-hold circuit for high-speed applications”, IEEE J. Solid-State Circuits, pp. 1461-146 (Oct. 1989).
G. Uehra, et al., “A 100 MHz A/D interface for PRML magnetic disk read channels”, IEEE J. Solid-State Circuits, pp. 1606-1613 (Dec. 1994).
A 10-b 20-Msample/s Low-Power CMOS ADC, Won Chul Song, Hae-Wook Choi; Sung-Ung Kwak and Bang-Sup Song,Senior Member, IEEE; IEEE Journal Solid-State Circuits, vol. 30, No. 5, May, 1995, pp. 514-517.
Lam Tuan T.
Limbach & Limbach L.L.P.
National Semiconductor Corporation
Nguyen Linh
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