Sample-and-hold circuit having reduced amplifier offset effects

Details Sample-and-hold circuit having reduced amplifier offset effects Sample-and-hold circuit having reduced amplifier offset effects

1998-04-06

2000-01-18

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

327 96, 327 95, H03K 1700, G11C 2702

Patent

active

060160675

ABSTRACT:
An integrated circuit sample-and-hold (S/H) circuit includes an amplifier offset compensation circuit for compensating for the D.C. offset of a buffer amplifier. The amplifier offset compensation circuit may include an offset determining circuit for determining an offset voltage generated by the buffer amplifier, and an offset correction circuit for generating an offset correction signal and coupling the offset correction signal to the buffer amplifier. The S/H circuit may include a substrate, a sampling capacitor formed on the substrate, and a first field-effect transistor (FET) formed on the substrate. The first FET may have a first conduction terminal for receiving the input signal, a second conduction terminal connected to the sampling capacitor, and a control terminal responsive to control signals for connecting the input signal to the first sampling capacitor during a sampling time and for disconnecting the input signal from the first sampling capacitor during a holding time. The first FET may further include a body creating a parasitic diode-connected to the first sampling capacitor. To address this parasitic diode, the circuit includes the buffer amplifier having an input connected to the first sampling capacitor and an output connected to the body of the first FET during the holding time. The offset of the buffer amplifier is compensated.

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