Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
2001-10-12
2003-09-30
Nguyen, Minh (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S096000, C327S563000, C341S122000
Reexamination Certificate
active
06628148
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a sample and hold circuit for holding an input voltage in response to a timing signal and outputting the holding voltage and, more particularly, to a sample and hold circuit which is suitable for use in a driving apparatus of an image display apparatus like a liquid crystal panel.
2. Related Background Art
A sample and hold circuit is used, for example, for a thin-film transistor driving circuit or the like of a liquid crystal panel. FIGS.
2
(
a
) and
2
(
b
) are circuit diagrams showing examples of constructions of conventional sample and hold circuits.
The sample and hold circuit shown in FIG.
2
(
a
) is a circuit of the parallel 2-latch/1-buffer amplifier type disclosed in JP-B-6-54418 and has an input terminal
1
to which an input voltage IN is supplied and a control terminal
2
to which a switching signal SW is supplied. Capacitors
4
a
and
4
b
for holding the input voltage IN are connected to the input terminal
1
through transfer gates (hereinafter, also referred to as “TGs”)
3
a
and
3
b
, respectively. The capacitors
4
a
and
4
b
are connected to the input side of a buffer amplifier (hereinafter, also referred to as “AMP”)
6
having a voltage amplification factor
1
through TGs
5
a
and
5
b
, respectively. The output side of the AMP
6
is connected to an output terminal
7
. The switching signal SW of the control terminal
2
is supplied as a control signal to the TGs
3
a
and
5
b
, inverted by an inverter
8
, and supplied as a control signal to the TGs
3
b
and
5
a
. Each of the TGs
3
b
,
5
a
, and
5
b
has the same construction as that of the TG
3
a.
According to such a sample and hold circuit, when the switching signal SW is at the “H” level, the TGs
3
a
and
5
b
are turned on and the TGs
3
b
and
5
a
are turned off, so that the input voltage IN at the input terminal
1
is charged into the capacitor
4
a
through the TG
3
a
. On the other hand, a voltage charged in the capacitor
4
b
is supplied to the AMP
6
through the TG
5
b
and outputted as an output voltage OUT from the AMP
6
to the output terminal
7
.
Subsequently, when the switching signal SW is set to the “L” level, the TGs
3
a
and
5
b
are turned off and the TGs
3
b
and
5
a
are turned on, so that the input voltage IN at the input terminal
1
is charged into the capacitor
4
b
through the TG
3
b
. On the other hand, a voltage charged in the capacitor
4
a
is supplied to the AMP
6
through the TG
5
a
and outputted as an output voltage OUT from the AMP
6
to the output terminal
7
.
As mentioned above, the input voltage IN is alternately charged into the two capacitors
4
a
and
4
b
in response to the switching signal SW and the charged voltage is outputted as an output voltage OUT through the AMP
6
.
On the other hand, the sample and hold circuit shown in FIG.
2
(
b
) is a circuit of the parallel 2-latch/2-buffer amplifier type disclosed in JP-A-11-249633 and constructed in a manner similar to that of FIG.
2
(
a
) except that the AMP
6
at the post stage of the TGs
5
a
and
5
b
in FIG.
2
(
a
) is deleted and AMPs
6
a
and
6
b
are provided between the capacitors
4
a
and
4
b
and the TGs
5
a
and
5
b
, respectively.
According to such a sample and hold circuit, when the switching signal SW is at the “H” level, the input voltage IN at the input terminal
1
is charged into the capacitor
4
a
through the TG
3
a
. On the other hand, the voltage charged in the capacitor
4
b
is supplied to the TG
5
b
through the AMP
6
b
and outputted as an output voltage OUT to the output terminal
7
through the TG
5
b.
Subsequently, when the switching signal SW is set to the “L” level, the input voltage IN at the input terminal
1
is charged into the capacitor
4
b
through the TG
3
b
. On the other hand, the voltage charged in the capacitor
4
a
is supplied to the TG
5
a
through the AMP
6
a
and outputted as an output voltage OUT to the output terminal
7
through the TG
5
a.
However, the conventional sample and hold circuits shown in FIGS.
2
(
a
) and
2
(
b
) have the following problems.
In the circuit of FIG.
2
(
a
), since the amplifier for both capacitors
4
a
and
4
b
is used in common as an AMP
6
, for example, when the switching signal SW is switched from “H” to “L”, the TG
5
a
is turned on and the capacitor
4
a
is connected to the input side of the AMP
6
. At this time, a parasitic capacitance on the input side of the AMP
6
, that is, an electrostatic capacitance of a gate of an MOS transistor constructing a non-inverting input terminal of the AMP
6
has been charged to the same voltage as the output voltage OUT just before the switching. The electrostatic capacitance of the gate of the MOS transistor at each non-inverting input terminal which gives the parasitic capacitance is equal to about {fraction (1/10)} of that of each of the capacitors
4
a
and
4
b
. The input voltage of the AMP
6
is influenced by the charges charged in the parasitic capacitor, the initial voltage held in the capacitor
4
a
changes, and an error is caused in the input voltage of the AMP
6
.
On the other hand, according to the circuit of FIG.
2
(
b
), since the voltages which are applied to the capacitors
4
a
and
4
b
through the TGs
3
a
and
3
b
are simultaneously inputted to the dedicated AMPs
6
a
and
6
b
, the error which is caused in the parasitic capacitor due to the common use of the amplifier as in case of the circuit of FIG.
2
(
a
) does not occur. However, since the two AMPs
6
a
and
6
b
are necessary, there is a problem of an increase in current consumption.
OBJECTS AND SUMMARY OF THE INVENTION
It is an object of the invention to provide a sample and hold circuit which does not cause an error due to a parasitic capacitance on the input side of an AMP and an increase in current consumption.
The invention is fundamentally made by paying attention to a construction in which an amplifier comprises: a differential input unit which generates a voltage according to a voltage difference between an input signal which is applied to a non-inverting input terminal and an input signal which is applied to an inverting input terminal; and a amplification output unit which amplifies an output voltage of the differential input unit. The invention is also based on an idea such that for the purpose of forming a pair of capacitors for holding an input voltage, a pair of differential input units are provided and a single amplification output unit which is shared by both of the differential input units is provided, thereby allowing the amplification output unit to alternately construct an amplifier together with both of the differential input units.
According to the first aspect of the invention, there is provided a sample and hold circuit comprising:
a pair of first switches whose operations are controlled by a switching signal and which alternately transfer input voltages to first and second nodes;
first and second capacitors which hold the input voltages transferred to the first and second nodes, respectively;
a first differential input unit which generates a voltage corresponding to a potential difference between the first node and an output terminal;
a second differential input unit which generates a voltage corresponding to a potential difference between the second node and the output terminal;
a pair of second switches which are controlled by the switching signal, transfer the voltage generated by the second differential input unit to a third node when the input voltage has been transferred to the first node, and transfer the voltage generated by the first differential input unit to the third node when the input voltage has been transferred to the second node; and
an output unit which outputs a voltage corresponding to the voltage at the third node to the output terminal.
The first and second differential input units have non-inverting input terminals and inverting input terminals. The non-inverting input terminals may be constructed by gates of fiel
Nguyen Minh
Oki Electric Industry CO Ltd.
Rabin & Berdo P.C.
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