Sample and hold circuit for a current mode pipelined...

Coded data generation or conversion – Analog to or from digital conversion – With particular solid state devices

Reexamination Certificate

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Details

C341S155000, C341S156000, C341S161000

Reexamination Certificate

active

07733254

ABSTRACT:
A pipelined current mode analog-to-digital converter, including: a plurality of stages each having a first sample and hold circuit configured to receive an analog signal having a current; the sample and hold circuit having at least first and second outputs; the first output having a current from a current copier configured to copy the analog signal; the second output having a current from a current mirror configured to mirror the analog signal; a current mode analog-to-digital converter configured to create a digital signal from the second output, the second output being connected to an input of the analog-to-digital converter; and a current mode digital-to-analog converter configured to convert the digital signal back to an analog signal, wherein an output of the digital-to-analog converter is subtracted from the first output of the sample and hold circuit.

REFERENCES:
patent: 5043732 (1991-08-01), Robertson
patent: 5990820 (1999-11-01), Tan
patent: 6313780 (2001-11-01), Hughes
patent: 7002505 (2006-02-01), Hughes
patent: 2003/0076253 (2003-04-01), Roovers et al.
patent: 2008/0117092 (2008-05-01), Wolf et al.
Switched-Current Circuits in Digital CMOS Technology with Low Charge-Injection Errors; Ganesh Kumar Balachandran and Phillip E. Allen, Fellow, IEEE; IEEE Journal of Solid-State Circuits, Vol. 37, No. 10, October 2002.
A CMOS Transistor-Only 8-b 4.5-Ms/s Pipelined Analog-to-Digital Converter Using Fully Differential Current-Mode Circuit Techniques; Chung-Yu Wu, Member, IEEE, Chih-Cheng Chen, Student Member, IEEE, and Jyh-Jer Cho; IEEE Journal of Solid-State Circuits, vol. 30, No. 5, May 1995.

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