Sample and hold circuit and method with common mode differential

Details Sample and hold circuit and method with common mode differential Sample and hold circuit and method with common mode differential

1997-10-22

1999-10-05

Young, Brian

Coded data generation or conversion

Sample and hold

327 94, H03M 302

Patent

active

059631562

ABSTRACT:
A sample and hold (S/H) circuit with common mode differential signal feedback for converting single-ended signals to differential signals includes a feedback loop for the input switched capacitor circuit to ensure that the input common mode voltage for the differential amplifier is maintained at a known value during the hold phase of operation. The feedback loop consists of a three-input error amplifier which monitors the two voltages at the differential input terminals of the differential amplifier in relation to the common mode reference voltage and generates a feedback voltage which is applied to the input terminals of the input switched capacitor circuit during the hold phase of operation. If both of the differential input terminal voltages are either more negative or more positive than the common mode reference voltage then the feedback voltage generated by the error amplifier is made more positive or negative, respectively.

REFERENCES:
patent: 5180932 (1993-01-01), Bengel
patent: 5418408 (1995-05-01), Mangelsdorf et al.
patent: 5581254 (1996-12-01), Rundel
Won-Chul Song, Hae-Wook Choi, Sung-Ung Kwak and Bang-Sup Song, "A 10-b 20-Msample/s Low-Power CMOS ADC", IEEE Journal of Solid-State Circuits, vol. 30, No. 5, May 1995, pp. 514-521.

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