Sample and hold circuit and method therefor

Details Sample and hold circuit and method therefor Sample and hold circuit and method therefor

1999-01-25

2001-03-06

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S091000, C327S259000

Reexamination Certificate

active

06198314

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to electronic circuitry, and more particularly to a sample and hold circuit.
BACKGROUND OF THE INVENTION
The telecommunications industry has created an infrastructure that can transfer information to one location to another location using many different kinds of technology and many different protocols. For example, information may be electronically communicated today using one or more of asymmetric digital subscriber line (ADSL) devices, cable modems, asynchronous transfer mode (ATM) hosts, V.90 modems, and a wide array of other protocols and devices. In order to enable effective communication of analog and/or digital information from one point to another using these resources, sample and hold circuits are routinely used within larger telecommunications systems. Therefore, sample and hold circuits are an integral and important component in telecommunication operations.
FIG. 1
illustrates a prior art circuit which may be used to sample and hold an analog input for use in telecommunications. Circuit
10
of
FIG. 1
has an analog in put
12
, a clock (CLK) input signal
11
, and a sample output
14
. The analog input
12
is a gated input and is not a continuously provided electrical signal. The input
12
is disconnected from transistor
20
during one half cycle of the clock
11
(either the logic high portion or the logic low portion of the clock's duty cycle). The circuit
10
is powered by a supply voltage (V
cc
)
16
and a ground voltage (GND)
18
.
In
FIG. 1
, the selectively gated analog input signal
12
is provided to a control electrode of an input bipolar transistor
20
.
The transistor
20
is serially coupled to a current source
22
through a node
21
. The current source
22
is coupled between the transistor
20
and the ground (GND)
18
as shown. The node
21
is also coupled to a control electrode of a transistor
26
and a first electrode of a capacitor
24
. The first current electrode of transistor
26
is coupled to the power supply voltage (V
cc
)
16
, and a second current electrode of transistor
26
provides the output signal
14
. A second electrode of the capacitor
24
is coupled to the ground (GND) line
18
as shown. The second current electrode of transistor
26
is also coupled through a current source
28
to the ground terminal
18
.
In operation, the node
21
is charged by transistor
20
, the current source
22
, and the capacitor
24
to a voltage value that is representative of the input
12
. Once this voltage is stable due to the settling of RC delays, skew, etc., the clock
11
switches the current source
22
off and disables the input to transistor
20
. After the disabling the clock
11
and the input
12
, this sampled signal on node
21
is substantially preserved over short time periods by the capacitor
24
. During this storage time, the voltage on node
21
is provided to the transistor
26
and the current source
28
to provide an output
14
. It is this output
14
that is held by a hold circuit for later processing.
The sample circuit illustrated in
FIG. 1
, which is used to perform a sample and hold function, is problematic for several reasons. First, if the input
12
is not gated, when the current source
22
in the circuit of
FIG. 1
is switched off by the clock signal
11
, then the input voltage
12
could rise above the sum of (1) the voltage on node
21
and (2) threshold voltage (Vt) drop. If the input voltage rises above this sum, then transistor
20
will be placed into a conducting state, thereby destroying the stored voltage on node
21
. For this reason, the input voltage
12
is gated or grounded when the current source
22
is disabled. Unfortunately, the switching of the input signal
12
is disadvantageous since it may introduce noise into the signal
12
. In addition, it takes time to turn the input
12
on and off and some time to wait for the input to stabilize before useful information is obtained in the circuit
10
. Therefore, the presence of the gated input
12
will slow device operation and result in degradation in performance. Also, the timing of the switching on and off of the current source
22
and the timing of the gating of the input
12
is critical and not easily set to an optimal point. Further, the switch circuitry added to the input line
12
adds additional circuitry to the circuit size.
In addition to the disadvantages associated with switching off the input voltage
12
during certain periods of time, the circuit
10
places two base-emitter diode paths between the input
12
and the output
14
. Even if the transistors
20
and
26
could be replaced with metal oxide semiconductor field effect transistors (MOSFETs), there would still be two threshold voltage drops between the input
12
and the output
14
. Such voltage drops are usually on the order of 0.5 volts to 1.2 volts each. Therefore, these threshold voltage drops or base emitter junctions would erode at least 1.0 volt from the rail-to-rail range of the output
14
. For low power supply voltages, this erosion could be 50% or more of the rail-to-rail range available between V
cc
16
and GND
18
. The result of this limitation is that noise margins are reduced or that V
cc
16
must be set to a sufficiently high level, or both. When V
cc
is raised, power consumption of the circuit
10
is increased. Therefore, the circuit of
FIG. 1
does not offer a low power sample and hold solution for low power applications.
In addition, the natural capacitance of the base-emitter junction of transistor
20
has an adverse affect on the speed of operation of circuit
10
. Therefore, the operation of circuit of
FIG. 1
is further degraded. Certain high communication rates cannot be supported by the circuit
10
.
In order to overcome the deficiencies of
FIG. 1
, the prior art has added significant numbers of components to circuit
10
. These components slightly mitigate the described deficiencies at the expense of huge increases in circuit size and, thus, cost. Another solution to the problems discussed above is to abandon the simple bipolar circuit of FIG.
1
and adopt a much more radical circuit design (e.g., use a complex interconnection of charge coupled devices or other more advanced devices) using more complex and expensive processing. Such progression to more complex devices and manufacturing processes means that it is much more difficult to manufacture a high yield product in a low cost environment. In addition, the more exotic a device is, the more difficult it is to integrate that device into other technologies.
Therefore, a need exists in the industry for a sample and hold circuit that reduces the disadvantages discussed above and does so preferably with reduced cost and improved ability to integrate the circuit with other active components.


REFERENCES:
patent: 5448189 (1995-09-01), Lacroix et al.
patent: 402137200 (1990-05-01), None
patent: 356007298 (1990-05-01), None
Munroe, etc., “2-&mgr;m, 1.6 mW Gated-gm Sampler with 72-dB SFDR for fs=160 Ms/s and fin=320.25 MHz” IEEE Journal of Solid State Circuits, vol. 33, No. 3, pp. 400-403, Mar. 1998.

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