Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Patent
1991-11-14
1993-10-12
Weldon, Ulysses
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
307353, 345208, G09G 336, G11C 2702
Patent
active
052529576
ABSTRACT:
A sample-and-hold circuit device includes a plurality of sampling field effect transistors for sampling an input signal in response to sampling pulses sequentially supplied from a sampling pulse transferring section, a plurality of charge-holding capacitors for respectively holding signal charges sampled by the sampling field effect transistors, and a plurality of compensating field effect transistors each having source and drain electrodes connected to a corresponding one of the charge-holding capacitors to save excess charges accumulatively stored together with signal charges in the charge-holding capacitors, wherein there is provided a pulse applying circuit for applying a driving pulse, which is obtained by inverting a sampling pulse applied to the gate of the sampling field effect transistor of one of the succeeding-stage sample-and-hold circuits, to the gate of the compensating field effect transistor of each sample-and-hold circuit.
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patent: 4492979 (1985-01-01), Ikeda
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patent: 4823027 (1989-04-01), Takahashi
patent: 5041823 (1991-08-01), Johnson et al.
patent: 5061920 (1991-10-01), Nelson
Analog MOS Integrated Circuits for Signal Processing, Chap. 7, Sec. 7.1 "Nonideal Effects in the Switches", Gregorian, et al., 1986.
Kabushiki Kaisha Toshiba
Saras Steve
Weldon Ulysses
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