Sample-and-hold circuit and CCD image sensor

Details Sample-and-hold circuit and CCD image sensor Sample-and-hold circuit and CCD image sensor

2011-07-26

2011-07-26

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S091000

Reexamination Certificate

active

07986170

ABSTRACT:
Noise is more effectively reduced in one circuit. When sampling and holding is performed, switching of an ON resistance of MOS transistors (MSH1and MSH2) that are for sampling is made in two or more stages according to speed of sampling. Here, a level adjustment circuit (20) is provided that generates sample-and-hold pulse signals (φSH1S and φSH2S), which vary voltage to enable switching the ON resistance of the MOS transistors (MSH1and MSH2), to be provided to gates of the MOS transistors (MSH1and MSH2).

REFERENCES:
patent: 6577168 (2003-06-01), Kakitani
patent: 2007/0013417 (2007-01-01), Lim
patent: 2009/0237120 (2009-09-01), Haraguchi
patent: 2010/0194441 (2010-08-01), Wang
patent: 61-8799 (1986-01-01), None
patent: 2-302999 (1990-12-01), None

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