Sample-and-hold circuit and A/D converter

Details Sample-and-hold circuit and A/D converter Sample-and-hold circuit and A/D converter

2001-11-06

2002-08-20

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S094000, C327S337000, C330S009000

Reexamination Certificate

active

06437608

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a sample-and-hold circuit and an A/D (Analog to Digital) converter using the sample-and-hold circuit, particularly to a sample-and-hold circuit using a completely differential type operational amplifier circuit and an A/D converter using the sample-and-hold circuit.
2. Description of the Related Art
Currently, there is an A/D (Analog to Digital) converter using a sample-hold-circuit including a completely differential type operational amplifier circuit. For example, the sample-hold-circuit is used in an A/D converter of a pipeline system. According to the A/D converter of the pipeline system, as shown by
FIG. 4
, sequential values are specified by A/D conversion cells Sn through S
1
for respective bits from MSB (Most Significant Bit) to LSB (Least Significant Bit) of n bits of PCM (Pulse Code Modulation) data. The A/D conversion cells S
k
(k=n, n−1, n−2, . . . 1) of the respective bits are provided with latches l
k1
, . . . l
kk−1
, l
kk
for successively shifting values of respectively specified bits and output values of the respective bits of MSB through LSB from latches at a final stage l
nn
, l
n−1n−1
, . . . , l
11
of the A/D conversion cells of the respective bits.
When the constitution of the respective A/D conversion cell S
k
is indicated by functional blocks, the respective A/D conversion cell S
k
is constituted by a comparator CO, a subtractor d
0
subtracting a voltage amount in correspondence with a determination result of “1” or “0” of the comparator CO from an input and a sample-and-hold circuit shO for sampling output voltage of the subtractor d
0
and outputting a double value thereof constituting 1 bit ADC (Analog to Digital Converter). At the comparator CO of an A/D conversion cell S
n
of 1st stage, predetermined reference voltage and input voltage are compared, when the input voltage is larger, MSB is set to be “1” and provided to a latch l
n1
, a voltage amount in correspondence with MSB “1” is subtracted from input voltage by the subtractor d
0
, the output of the subtractor d
0
is doubled by the sample-and-hold circuit sh and output voltage in correspondence with carrying the digit of the output of the subtractor d
0
by 1 bit, is provided to an A/D conversion cell S
n−1
, at a next stage. Similarly, at A/D conversion cells S
n−1
, S
n−2
, S
l
at and after the next stage, bits lower than MSB are determined. Values determined by the A/D conversion cells S
n
, S
n−1
, S
l
in accordance with a predetermined sampling clock, are shifted at respective latch stages in accordance with a sampling clock, not illustrated, and values of respective bits of MSB through LSB are outputted from the final stage.
In an actual A/D conversion cell, there is used a sample-and-hold circuit having a completely differential type operational amplifier circuit and is constructed by a constitution having functions of the subtractor d
0
and the sample-and-hold circuit sh
0
. According to the constitution, as shown by
FIG. 5
, a first switch capacitor net CS
1
is provided between a first input terminal IN
1
constituting a negative input terminal of a completely differential type operational amplifier circuit
51
and a first output terminal OUT
1
constituting a positive output terminal thereof and a first reset switch RS
1
is provided between the first input terminal IN
1
and the first output terminal OUT
1
. The first switch capacitor net CS
1
is constituted by capacitors C
1
and C
2
one terminal of each of which is connected to the first input terminal IN
1
, a switch SW
1
for selectively connecting other terminal of the capacitor C
1
to an input terminal IN
0
of the sample-and-hold circuit, a reference voltage terminal Ref or the first output terminal OUT
1
and a switch SW
2
for selectively connecting other terminal of the capacitor C
2
to the input terminal IN
0
of the sample-and-hold circuit shl, a reference voltage terminal Ref′ or the first output terminal OUT
1
constituting the positive output terminal of the completely differential type operational amplifier circuit
51
. A second switch capacitor net CS
2
similar to the first switch capacitor net CS
1
is provided between a second input terminal IN
2
constituting a positive input terminal of the completely differential type operational amplifier circuit
51
and a second output terminal OUT
2
constituting a negative output terminal and a second reset switch RS
2
is provided between the second input terminal and the second output terminal. The second switch capacitor net CS
2
is constituted by capacitors C
1
′ and C
2
′ having an equal capacitance value, one terminal of each of which is connected to the second input terminal IN
2
, a switch SW
3
for selectively connecting other terminal of the capacitor C
1
′ to an input terminal IN
0
′ constituting other of differential input terminals of the sample-and-hold circuit, the reference voltage terminal Ref′ and the second output terminal OUT
2
, and a switch SW
4
for selectively connecting other terminal of the capacitor C
2
′ to an input terminal IN
0
′ constituting other of the differential input terminals of the sample-and-hold circuit sh
1
, the reference voltage terminal Ref and the second output terminal OUT
2
constituting a negative output terminal of the completely differential type operational amplifier circuit
1
.
As shown by
FIG. 6
, the sample-and-hold circuit sh
1
constitutes the A/D conversion cell S
k
by connecting an input terminal of the comparator CO to the input terminals IN
0
and IN
0
′. During a hold period, mentioned later, the above-described subtracting operation can be carried out by controlling the switches SW
1
and SW
2
of the first switch capacity net CS
1
and the switches SW
3
and SW
4
of the second switch capacity net CS
2
by the output of the comparator CO. The A/D conversion cell S
k
is connected to the A/D conversion cell S
k−1
at a successive stage by connecting the similar input terminals IN
0
and IN
0
′ of the sample-and-hold circuit shl and the comparator CO of the A/D conversion cell S
k−1
to the output terminals OUT
1
and OUT
2
of the sample-and-hold circuit sh
1
to thereby constitute the A/D converter of the pipeline system shown in FIG.
4
.
Details of operation of the sample-and-hold circuit sh
1
are as follows.
During a sample period, as shown by
FIG. 7A
, the first and the second reset switches RS
1
and RS
2
are made ON and in the first switch capacitor net CS
1
, the capacitors C
1
and C
2
are conducted between the input terminal IN
0
and the input terminal IN
1
in parallel. Also in the second switch capacitor net CS
2
, the capacitors are connected similarly. When voltage of the input terminal IN
1
is designated by notation Vt, input voltage inputted to the input terminal IN
0
is designated by notation Vin and the capacitance values of the capacitors C
1
and C
2
are equally designated by notation C, a total sum Q of electric charge stored in the capacitors C
1
and C
2
, is represented as follows.
Q
=2
C
(
V
in
−V
i
)  (1)
During the hold period, as shown by
FIG. 7B
, the first and the second reset switches RS
1
and RS
2
are made OFF, in the first switch capacitor net CS
1
, in accordance with the output of the comparator CO, the other terminal of the capacitor C
1
is blocked from the input terminal IN
0
and conducted to the reference voltage terminal Ref, and the other terminal of the capacitor C
2
is blocked from the input terminal IN
0
and conducted to the first output terminal OUT
1
or the other terminal of the capacitor C
2
is blocked from the input terminal IN
0
and conducted to the reference voltage terminal Ref′ and the other terminal of the capacitor C
1
is blocked from the input terminal IN
0
and conducted to the first output terminal OUT
1
. The second switch capacitor net CS
2
is connected similarly.

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