Sample-and-hold circuit

Details Sample-and-hold circuit Sample-and-hold circuit

1986-09-29

1988-03-01

Shoop, Jr., William M.

Electrical transmission or interconnection systems

Switching systems

307106, 307353, 333173, 328151, H03H 1112

Patent

active

047288116

ABSTRACT:
A sample-and-hold circuit has an impedance converter, a first switch, an amplifier, an input circuit for receiving an input signal and supplying an output signal corresponding to the input signal to the amplifier, through the impedance converter and the first switching means, output-holding capacitor coupled between the input and output terminals of the amplifier, and a feedback circuit coupled between the output terminal of the amplifier and the input terminal of the impedance converter. The input circuit and the feedback circuit are a first switched capacitor and a second switched capacitor, respectively.

REFERENCES:
patent: 3671782 (1972-06-01), Wittlinger et al.
patent: 3818246 (1974-06-01), Hellwarth et al.
patent: 4315227 (1982-02-01), Fleischer et al.
patent: 4352070 (1982-09-01), Beauducel et al.
patent: 4404479 (1983-09-01), Toyomaki
patent: 4446438 (1984-05-01), Chang et al.
patent: 4484089 (1984-11-01), Viswanathan
patent: 4520283 (1985-05-01), Sasaki et al.
patent: 4531106 (1985-07-01), Ganesan
patent: 4543546 (1985-09-01), Hariharam
patent: 4546324 (1985-10-01), Bingham et al.
patent: 4558292 (1985-12-01), Sasaki et al.
patent: 4591736 (1986-05-01), Hirao et al.
patent: 4600904 (1986-07-01), Shumaker
"A Precision FET-Less Sample-and-Hold With High Change-to-Droop Current Ratio", by IEEE, vol. SC--13, No. 6, Dec. 1978.

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