Sample-and-hold circuit

Details Sample-and-hold circuit Sample-and-hold circuit

1991-10-30

1993-09-07

Zazworsky, John

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307257, 307321, 307491, G11C 2702, H03K 1776

Patent

active

052432351

ABSTRACT:
A sample-and-hold circuit comprising a diode circuit including four diodes connected in series, an input circuit connected to a first node of the first and third diodes and a second node of the second and fourth diodes, first and second output terminals connected to a third node of the first and second diodes and a fourth node of the third and fourth diodes, two capacitors connected to the third and fourth nodes, respectively, and a current mirror circuit having a first terminal connected to the input circuit, a second terminal connected to the first node, and a third terminal connected to the second node, for supplying to the second and third terminals, a DC bias current and a dynamic current corresponding to the slew rate of the input signal flowing through the first terminal of the current mirror circuit. The diode circuit charges the capacitor with the output current supplied from the current mirror circuit in accordance with the input signal, thereby to sample the input signal, and holds the charge in the capacitor upon completion of the charging of the capacitor, thereby to hold the input signal.

REFERENCES:
patent: 4659946 (1987-04-01), Agoston
patent: 4879478 (1989-11-01), Gershon
patent: 5089720 (1992-02-01), Gloaguen
Electronic Design, vol. 35, No. 5, pp. 71-74, Mar. 5, 1987, F. Goodenough, "ISSCC: Analog".
John Markus, Sourcebook of Electronic Circuits, pp. 81-84 and p. 82, McGraw-Hill Book Company.

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