Sample-and-hold circuit

Details Sample-and-hold circuit Sample-and-hold circuit

1993-03-30

1995-09-12

Wambach, Margaret Rose

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

H03K 1768

Patent

active

054499607

ABSTRACT:
An input terminal is connected to bases of first and second transistors. Collectors of the first and fourth transistors are connected to a power-source terminal. Collectors of the second and third transistors are grounded. A base of the third transistor is connected to an emitter of the first transistor. A base of the fourth transistor is connected to an emitter of the second transistor. One terminal of the capacitor is grounded and the other terminal thereof is connected to emitters of the third and fourth transistors and an input of an output buffer whose output is connected to an output terminal. A collector of a fifth transistor is connected to the power-source terminal and a base thereof is connected to the output terminal. A collector of a sixth transistor is grounded and a base thereof is connected to the output terminal. A first constant-current source is connected to an emitter of the fifth transistor and a base of the fourth transistor. A second constant-current source is connected to an emitter of the sixth transistor and the base of the third transistor. A third constant-current source is connected to the emitter of the first transistor and turned on at a sampling time. A fourth constant-current source is connected to the emitter of the second transistor and turned on at the sampling time.

REFERENCES:
patent: 5124576 (1992-06-01), Vensen
Wakayama, Myles H. et al, "FA12.5 A 1.2.mu.m BICMOS 100MHz Sample-and-Hold Circuit with a . . . Gate", 1992 IEEE International Solid-State Circuits Conference, pp. 200-201, and 282.

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