Sample-and-hold circuit

Details Sample-and-hold circuit Sample-and-hold circuit

2001-03-29

2002-06-18

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S096000, C341S122000

Reexamination Certificate

active

06407592

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a sample-and-hold circuit that stores the electric charge corresponding to an input voltage in a capacitor, and holds the potential thereof, and particularly to a sample-and-hold circuit that reduces the charge leakage due to the switches connected to the electrode of the capacitor, and suppresses the reduction in the held voltage.
2. Description of the Related Art
FIG. 4
is a circuit diagram for a capacitor array type D/A conversion circuit using a conventional sample-and-hold circuit.
This sample-and-hold circuit stores the charge corresponding to the voltage input from an input terminal VR in a capacitor C
3
, and holds the potential thereof. The held potential is amplified by an amplifier
10
connected to the capacitor C
3
, and the amplified voltage is output from an output terminal Vout to the outside.
The capacitor that stores the charge corresponding to the voltage input from the outside and holds the potential thereof is referred to as a “hold capacitor”.
The operation of this conventional capacitor array type D/A conversion circuit will be described below. First, for initialization (reset), all of the one ends of the capacitors C
0
to C
2
are connected to the ground GND by switches SW
0
to SW
2
, and a N-channel MOS transistor TN
1
is turned on. Then, the amount of the charges which have been stored in the capacitors C
0
to C
3
becomes zero.
Next, in response to the digital signals input as signals to be D/A converted, one ends of the capacitors C
0
to C
2
are connected to a reference voltage terminal VR by the SW
0
to SW
2
switches, and then a N-channel MOS transistor TN
1
is turned off. Here, for example, when one end of the capacitor C
0
is connected to the ground GND by the switch SW
0
, the one ends of the capacitors C
1
and C
2
are connected to a reference voltage terminal VR by the switches SW
1
and SW
2
, and the N-channel MOS transistor TN
1
is turned off, a voltage output from the output terminal Vout is given by the following equation.
Vout=(Q
3
/C
3
)={(C
1
+C
2
)/C
3
}×VR  (1)
where, C
1
to C
3
denotes the capacitances of the capacitors C
1
to C
3
, respectively, and Q
3
denotes the amount of the charge stored between both ends of the capacitor C
3
.
FIG. 5
is a circuit diagram for a switching comparator using a sample-and-hold circuit in accordance with another conventional example.
In
FIG. 5
, a sample-and-hold circuit is comprised of a capacitor C
4
, an inverter I
1
, and a N-channel MOS transistor TN
3
. By adding N-channel MOS transistors TN
2
and TN
4
to such a sample-and-hold circuit, a switching comparator is formed.
The operation of the switching comparator shown in
FIG. 5
will be described using a timing chart shown in FIG.
6
.
First, in a time period T
1
, the N-channel MOS transistors TN
2
and TN
3
are turned on, and the N-channel MOS transistor TN
4
is turned off. The capacitor C
4
is thereby initialized while an input voltage V
1
is applied.
Then, in a time period T
2
, the N-channel MOS transistors TN
2
and TN
3
are turned off, and the N-channel MOS transistor TN
4
is turned on. As a result, the output of the inverter I
1
varies in response to the potential difference between the input voltage V
1
and an input voltage V
2
. If V
1
is larger than V
2
, an “H” level, that is, a power supply voltage VDD is output from the inverter I
1
. On the other hand, if V
1
is smaller than V
2
, an “L” level, that is, a GND level is output from the inverter I
1
. In this way, the switching comparator compares magnitudes between input voltages V
1
and V
2
, and outputs an “H” level or an “L” level.
Hereafter, after the time period T
3
, similar operations to the above-described time periods T
1
and T
2
are repeated.
FIG. 7
is a circuit diagram for a successive comparison type A/D conversion circuit using the above-described switching comparator.
In this A/D conversion circuit, each of N-channel MOS transistors TN
11
, TN
12
, TN
13
, etc. corresponds to the N-channel MOS transistor TN
4
of the above-described switching comparator. The connection nodes in a ladder resistor comprising a plurality of resistors R are connected to the plurality of N-channel MOS transistors TN
11
, TN
12
, TN
13
etc. Each of the plurality of N-channel MOS transistors selectively selects the voltage produced by the ladder resistor. Herein, a capacitor C
4
stores the charge given by the following equation.
Q=C
4
×(Vin−Vb)  (2)
where, Vb denotes the input voltage of the inverter I
1
when the capacitor C
4
has been initialized.
The operation of the A/D conversion circuit shown in
FIG. 7
will be described using a timing chart shown in FIG.
8
.
First, in a time period TO, the N-channel MOS transistors TN
2
and TN
3
are turned on, and all of the N-channel MOS transistors TN
11
, TN
12
, TN
13
, etc. are turned off. The capacitor C
4
is thereby initialized while an analog signal Vin to be A/D converted is applied to.
Then, in a time period T
1
, the N-channel MOS transistors TN
2
and TN
3
are turned off, and the N-channel MOS transistor TN
11
is turned on. As a result, the output of the inverter I
1
varies in response to the potential difference between the input voltage Vin and a reference voltage VR
1
. If VR
1
is smaller than Vin, an “H” level is output from the inverter I
1
. On the other hand, if VR
1
is larger than Vin, an “L” level is output. In this manner, the switching comparator compares magnitudes between the input voltage Vin and the reference voltage VR
1
, and outputs an “H” level or an “L” level.
Next, in a time period T
2
, the N-channel MOS transistors TN
2
and TN
3
are turned off, and the N-channel MOS transistor TN
12
is turned on. As a result, the output of the inverter I
1
varies in response to the potential difference between the input voltage Vin and a reference voltage VR
2
. If VR
2
is smaller than Vin, an “H” level is output from the inverter I
1
. On the other hand, if VR
2
is larger than Vin, an “L” level is output. The switching comparator thus compares magnitudes between an input voltage Vin and the reference voltage VR
2
, and outputs an “H” level or an “L” level.
The same operation is performed for each time period after a time period T
3
. N-channel MOS transistors from a N-channel MOS transistor TN
13
onward are successively turned on, reference voltages from a voltage VR
3
onward are successively input, and reference voltages are successively compared with the input voltage Vin.
FIG. 9
is a circuit diagram for a sample-and-hold circuit in accordance with a third conventional example.
In this sample-and-hold circuit, the voltage input from an input terminal Vin is amplified by an amplifier
11
, and the amplified voltage is output from an output terminal Vout. Also, the charge corresponding to the voltage input from the input terminal Vin is stored in a capacitor C
5
, and the potential is held by turning off a N-channel MOS transistor TN
5
. Even after the N-channel MOS transistor TN
5
has been turned off, the held potential continues to be output.
In this manner, in each of these first to third conventional examples, the charge corresponding to the voltage input from the outside is stored in the capacitor, and thereby the potential thereof is held. However, even if the switches connected to the capacitor are turned off, the charge stored in the capacitor leaks as leakage currents via the switches.
Specifically, for example, in the first conventional example shown in
FIG. 4
, even if the N-channel MOS transistor that constitutes a switch is in the OFF state with its gate voltage being 0V, the charge stored in the capacitor C
3
leaks as leakage currents via the N-channel MOS transistor TN
1
. Likewise, in the second conventional example shown in
FIG. 5
, the charge stored in the capacitor C
4
leaks as leakage currents via the N-channel MOS transistor TN
3
that is in the OFF state, and in the third conventional examp

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