Coded data generation or conversion – Sample and hold
Reexamination Certificate
1998-10-26
2001-07-17
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Sample and hold
C327S094000
Reexamination Certificate
active
06262677
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to the field of electronic devices and specifically to a method and apparatus for providing high speed sample-and-hold capabilities.
BACKGROUND OF THE INVENTION
A goal in sample-and-hold circuits is to facilitate high-frequency operation while providing low power consumption. Additionally, it is sometimes desirable to perform one or more mathematical functions on a signal or signals before the resultant signal is sampled and held. The mathematical function may be any combination of multiplication, division, addition or subtraction. Implementing the mathematical function or functions and the sample-and-hold functions separately is typically area and power inefficient. It may be, therefore, desirable to combine the various operations in an efficient way without sacrificing accuracy, speed or power.
One approach to combining these functions is to use a differential gain stage, which performs the mathematical function, to drive a sample-and-hold circuit comprising a CMOS switch and a storage device. A problem with this approach is that the CMOS switch tends to have injection into the storage device, which is level dependant. This level dependency generally degrades the performance of the sample-and-hold circuit. In addition, high speed designs will often preclude the clock from being at levels suitable for proper CMOS operation, because, for example, the voltage level will often be limited to decrease propagation time. In such circumstances, the use of a CMOS switch may be inappropriate because the voltage swing of the signal may not be adequate to turn the switch on and/or off.
Another approach is to use a differential gain stage to drive bipolar junction transistors acting as a switch for the storage device. The bipolar junction transistors often consist of diodes which level shift up and down during sample mode. A problem with this approach is that these switch designs are inefficient and consume power.
Still another approach consists of a differential gain stage having a buffer driver off the load, which directly drives the storage element. In hold mode, the load is directly pulled down while depriving current to the driver. A problem with this approach is that the circuitry required to pull down the load tends to slow the operation of the circuit. Operation at higher speeds typically requires loads with low resistance. Using loads with low resistance generally requires a larger current to pull the voltage of the load down sufficiently to enter hold mode. Thus, this approach requires high current levels for high speed operation. In addition, the voltage on the load may be influenced by variations in the input signal. These variations may propagate to the storage element and corrupt the stored signal.
SUMMARY OF THE INVENTION
In accordance with the teachings of the present invention, a differential sample-and-hold circuit is provided that eliminates or substantially reduces problems associated with prior approaches.
According to one embodiment of the present invention, a differential sample-and-hold circuit comprises a differential gain stage having a control transistor and an output node. The differential gain stage further comprises a primary load coupled between the control transistor and the output node. A hold control circuit is coupled to the base of the control transistor, the hold control circuit operable to effect a reduction of the base voltage of the control transistor and a corresponding reduction of the voltage at the output node of the differential gain stage.
The present invention has several important technical advantages. The invention facilitates combining mathematical and sample-and-hold functions without sacrificing accuracy, speed or power. Controlling the voltage at the output node of the differential gain stage through a voltage drop initiated by the hold control circuit, rather than at the primary load of the differential gain stage, facilitates the use of a low-level current source driving the hold control circuit. The invention, therefore, facilitates lower power consumption due to the low-level current sources used. Scaling the current in an integrated circuit application typically results in smaller device size. Smaller device size provides smaller parasitic capacitances. Lower parasitics, in turn, result in increased device speed. By minimizing the parasitics at the critical nodes, the invention optimizes the speed of the device.
The invention provides a method of switching between sample mode and hold mode by controlling the voltage at the output node of the differential gain stage through choice of the load in the hold control circuit and a current source driving that load. The common-mode sample-and-hold output is determined primarily by the values of the primary load, transconductance element and current source of the differential gain stage. The present invention, therefore, provides a method of setting the common-mode sample-and-hold output voltage which is independent of the method of switching between sample mode and hold mode.
Providing a clamping circuit capable of reducing the gain of the differential gain stage in response to a reduction in voltage at the output node effectively isolates the storage circuit from the rest of the circuit during hold mode. This prevents the input signal from corrupting the stored analog sample. Additionally, the clamping circuit acts to hold the voltage at the output node at or near the voltage on the storage element. Thus, the base voltage of the emitter-follower remains close to its turn-on value, increasing switching speed between sample and hold modes. Furthermore, holding the voltage of the output node at or near the voltage on the storage element ensures that the collector voltage of the gain stage transistor does not fall below that transistor's base voltage. This avoids saturating the gain stage transistor, which would otherwise decrease device speed. Another advantage is that this circuit allows a greater range common mode input voltages because no level shifting of the common mode signal is required.
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Kiriaki Sami
Wolfe Mark A.
Brady III Wade James
Jean-Pierre Peguy
Swayze, Jr. W. Daniel
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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