Sample and hold circuit

Details Sample and hold circuit Sample and hold circuit

1976-04-01

1978-01-03

Zazworsky, John

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307242, 328151, 328165, G11C 2702

Patent

active

040669190

ABSTRACT:
An electronic circuit suitable to be fabricated in monolithic integrated circuit form for producing at an output terminal an output signal for a predetermined time period of which the value thereof corresponds to the value of a periodically sampled, time varying, input signal applied at an input terminal. The circuit comprises two identical and parallel channels connected between the input and the output terminals such that one channel is in a sample mode while the other channel is in a hold mode and vice versa. Each channel includes a pair of operational amplifiers operatively coupled to an integrating capacitor. The dual channel system provides self compensation for offset voltage and common mode rejection. Thus, no manual nulling adjustment is required. Because self compensation is renewed each sample/hold cycle, the circuit is substantially insensitive to temperature variations over a broad range of temperatures.

REFERENCES:
patent: 3226650 (1965-12-01), Higbie
patent: 3820033 (1974-06-01), Iwata

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