Sample-and-hold circuit

Details Sample-and-hold circuit Sample-and-hold circuit

1993-05-18

1995-04-25

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

327 95, 327391, G11C 2702, H03K 17687

Patent

active

054102693

ABSTRACT:
A sample-and-hold circuit, capable of charging and discharging its holding capacitor quickly regardless of a voltage of an analog input signal and an output impedance of an analog driving source, includes a pre-sampling capacitor and at least one CMOS inverter. Before the holding capacitor holds the sampled signal, the pre-sampling capacitor stores the signal level of the analog input signal, and then the CMOS inverter charges and discharges the one side of the holding capacitor according to the stored voltage in the pre-sampling capacitor. Since the one side of the holding capacitor is charged and discharged by the CMOS inverter thus controlled, the sample-and-hold circuit can operate with high speed and handle a wide range of the analog input signal.

REFERENCES:
patent: 4523107 (1985-06-01), Peterson
patent: 4656429 (1987-04-01), Masuda et al.
patent: 4691125 (1987-09-01), Rybicki
patent: 4695748 (1987-09-01), Kumamoto
patent: 4764689 (1988-08-01), Thommen
patent: 4845383 (1989-07-01), Iida
patent: 4978872 (1990-12-01), Morse et al.
patent: 5180930 (1993-01-01), Mayes
Title page and pp. 296-299, 616-619, and 654-655 of VLSI Design Techniques For Analog And Digital Circuits, author: Randall L. Geiger et al, published by McGraw-Hill Publishing Company, New York, 1990.

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