Sample-and-hold circuit

Details Sample-and-hold circuit Sample-and-hold circuit

1986-02-04

1987-09-15

Chin, Tommy P.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

328151, 307353, 307475, H04N 544, G11C 2702

Patent

active

046943412

ABSTRACT:
A sample-and-hold circuit is provided wherein an input signal is fed via a first gate element to one end of a first capacitor whose other end is alternately grounded, the one end of the first capacitor being connected via a second capacitor to a gate (or base) of a source (or emitter) follower transistor to obtain an output from the source (or emitter) of the transistor which is connected via a second gate element to one end of the first capacitor, while the gate (or base) of the transistor is connected via a third gate element to a DC voltage supply having a predetermined voltage value, and the second and third gate elements are turned on during a first period of the input signal so that a voltage corresponding to the gate-source (or base-emitter) offset voltage of the transistor is stored in the second capacitor, while the first gate element is turned on during a second period of the input signal to produce an output signal equivalent in level to the input signal.

REFERENCES:
patent: 4066919 (1978-01-01), Huntington
patent: 4331894 (1982-05-01), Gregorian et al.
patent: 4404479 (1983-09-01), Toyomaki
patent: 4429239 (1984-01-01), Gay
patent: 4560890 (1985-12-01), Masuda et al.
Sample-Hold Circuit is Inexpensive and Stable, Electronic 14, Jul. 4, 1968, p. 94.

Affiliated with

Also associated with

Rating

Sample-and-hold circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Sample-and-hold circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Sample-and-hold circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1389083