Sample-and-hold circuit

Details Sample-and-hold circuit Sample-and-hold circuit

1987-04-14

1989-04-25

Zazworsky, John

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307267, 307606, 307605, 328151, H03K 506, G11C 2702

Patent

active

048251038

ABSTRACT:
A sample-and-hold circuit distinguished by its lack of a storage capacitor. The circuit includes a delay line and a signal following circuit coupled to the delay line which is synchronized with the delay line's propagation rate. In several embodiments of the invention a multi-tap delay line is used, and the signal following circuits variously include an electronic switch or linear interpolation circuits. In several other embodiments of this invention a gate of a FET is used as the delay line, and the signal following circuits include the drain and source of the FET. By substituting a delay line and signal following means for a storage capacitor, extremely fast sample-and-hold circuits may be obtained.

REFERENCES:
patent: 2912601 (1959-11-01), Slatten, Jr.
patent: 3278846 (1966-10-01), Patten et al.
patent: 3906400 (1975-09-01), Gooding et al.
patent: 4227160 (1980-10-01), Tamori et al.
patent: 4291286 (1981-09-01), Wagner
J. L. Anderson, Single-Pulse Sampling Circuit, IBM Tech. Disc. Bulletin, vol. 9, No. 4, Sep. 1966, p. 381.
One Gigasample per Second Transient Recorder: A Performance Demonstration IEEE Trans. on Nuclear Science, vol. NS30, No. 1, Feb. 1983, pp. 278-282.

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