Sample and hold circuit

Details Sample and hold circuit Sample and hold circuit

1980-05-30

1983-07-12

Zazworsky, John

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307577, 307584, H03K 17687, G11C 2702

Patent

active

043933181

ABSTRACT:
A sample and hold circuit for holding a sampled voltage, having a first MOS transistor for sampling the input voltage and a holding capacitor for holding the sampled voltage, and further comprising a second MOS transistor. The source and the drain of the second transistor are both connected to the output terminal of the circuit. The gate-source capacitance of the first MOS transistor is the sum of the gate-source and gate-drain capacitances of the second MOS transistor. When a voltage for turning on or off the first MOS transistor is applied to the gate of the first MOS transistor, the second MOS transistor is turned off or on respectively. The effect of this invention is that the sampled voltage can be held constant while turning off the first MOS transistor.

REFERENCES:
patent: 3586880 (1971-06-01), Fitzwater, Jr.
patent: 3594589 (1971-07-01), Hall
patent: 3764921 (1973-10-01), Huard
patent: 4010388 (1977-03-01), Alvarez, Jr.
patent: 4048525 (1977-09-01), Goldberg et al.
patent: 4176289 (1979-11-01), Leach et al.

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