Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
2003-07-01
2004-10-19
Nguyen, Minh (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S337000, C341S122000, C341S144000
Reexamination Certificate
active
06806745
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an amplifier circuit of high precision type having a sample-and-hold function, relates to pipelined A/D (analog-to-digital) and D/A (digital-to-analog) converters respectively using such an amplifier circuit of high precision type, and particularly relates to the circuits and converters realizing low power consumption and high operational speed.
BACKGROUND OF THE INVENTION
Conventionlly, when realizing an amplifier circuit of high precision type having a sample-and-hold function (hereinafter referred to as SHA circuit), it was necessary to use an operational amplifier having a high DC gain. According to the operational amplifier having such a high DC gain, a plurality of operational amplifiers are connected with each other in a series manner. For example, IEEE Symposium on VLSI Circuits, pages 94 to 95, published in 1996, discloses an SHA circuit in which two operational amplifier stage are used and a pipelined A/D converter using such an SHA circuit. The following description deals with the operational principle of the SHA circuit with reference to FIG.
13
.
The SHA circuit shown in
FIG. 13
is provided with an operational amplifier
100
, capacitors
106
p
and
106
m
that carry out the samplings of respective input signals from voltages VINP and VINM, capacitors
107
p
and
107
m
via which respective negative feedback are formed in the operational amplifier
100
, phase compensation capacitors
104
p
and
104
m
, and a plurality of switches
103
,
105
p
,
108
p
,
109
p
,
105
m
,
108
m
, and
109
m
which are respectively realized by an analog switch. The operational amplifier
100
is realized by first and second operational amplifier stages
101
and
102
that are connected with each other in a series manner so as to respectively carry out the sample-and-hold operation, the amplification, and addition and subtraction operations with respect to the analog signal with high precision. The phase compensation capacitors
104
p
and
104
m
compensate the deterioration of phase margin occurred when the first and second operational amplifier stages
101
and
102
are connected with each other in a series manner.
According to the SHA circuit having the above circuit configuration, in a sampling phase &phgr;s during which the input signal is subjected to the sampling, (a) two pairs of input-output terminals of the first operational amplifier stage
101
are connected with each other (short-circuited) via the switches
105
p
and
105
m
, respectively and (b) two output terminals of the second operational amplifier stage
102
are connected with each other (short-circuited) via the switch
103
. The switch
108
p
is operated so that the voltage VINP is applied to an electrode of the capacitor
106
p
. The switch
109
p
is operated so that a reference voltage VREF is applied to an electrode of the capacitor
107
p
which is provided on the upper stream side of the feedback during the negative feedback. The switch
108
m
is operated so that the voltage VINM is applied to an electrode of the capacitor
106
m
on the input terminal side. The switch
109
m
is operated so that the reference voltage VREF is applied to an electrode of the capacitor
107
m
which is provided on the upper stream side of the feedback during the negative feedback. This allows that the capacitor
106
p
carries out the sampling of one input signal from the voltage VINP, the capacitor
106
m
carries out the sampling of another input signal from the voltage VINM, and the capacitors
107
p
and
107
m
carry out the sampling of the difference between the reference voltage VREF and an offset voltage (1/f noise) of the first operational amplifier stage
101
, respectively.
In general, the gate area of an input transistor in the second operational amplifier stage
102
is several times to several tens times as large as that of the first operational amplifier stage
101
. This causes the offset voltage and the 1/f noise to be smaller in the second operational amplifier stage
102
than in the first operational amplifier stage
101
. The offset voltage and the 1/f noise of the second operational amplifier stage
102
that are viewed from the input terminals of the first operational amplifier stage
101
are equal to the division of the offset voltage of the second operational amplifier stage
102
by the DC gain A1 of the first operational amplifier stage
101
. Accordingly, in most cases, the offset voltage and the 1/f noise are negligible.
In the next hold phase &phgr;h, (a) the two pairs of input and output terminals of the first operational amplifier stage
101
are cut off by the switches
105
p
and
105
m
, respectively and (b) the two output terminals of the second operational amplifier stage
102
are also cut off by the switch
103
. The switch
108
p
is operated so that the reference voltage VREF is applied to the capacitor
106
p
. The switch
109
p
is operated so that a voltage VOUTP which is one output of the second operational amplifier stage
102
is applied to the electrode of the capacitor
107
p
which is provided on the upper stream side of the negative feedback. The switch
108
m
is operated so that the reference voltage VREF is applied to the electrode of the capacitor
106
m
on the input terminal side. The switch
109
m
is operated so that a voltage VOUTM which is another output of the second operational amplifier stage
102
is applied to the electrode of the capacitor
107
m
which is provided on the upper stream side of the negative feedback. In the sampling phase &phgr;s, the calculation is carried out in accordance with the conservation law of electric charges between the electric charges charged by the capacitor
106
p
and the electric charges charged by the capacitor
107
p
. Also, the calculation is carried out in accordance with the conservation law of electric charges between the electric charges charged by the capacitor
106
m
and the electric charges charged by the capacitor
107
m
. The calculations allow to output a voltage (VOUTP−VOUTM) that is the difference between the two output terminals of the second operational amplifier stage
102
.
FIG. 14
is a block diagram showing a circuit configuration of a conventional pipelined A/D converter. In the pipelined A/D converter, a sample-and-hold circuit
111
that holds voltages VINP and VINM of the input signal, and a plurality of sub-stages STG
11
, STG
12
, STG
13
, and STG
14
are connected with each other in this order in a series manner. Each of the sub-stages is connected with a digital error correction circuit (logic)
119
. The sub-stage STG
11
is composed of a sub-D/A converter
112
and a sub-A/D converter
113
. The sub-stage STG
12
is composed of a sub-D/A converter
114
and a sub-A/D converter
115
. The sub-stage STG
13
is composed of a sub-D/A converter
116
and a sub-A/D converter
117
. The sub-stage STG
14
is composed of only a sub-A/D converter
118
.
The sample-and-hold circuit
111
, and the sub stages STG
12
and STG
14
are operated in response to a clock signal CLK. The sub-stages STG
11
and STG
13
are operated in response to an inverted signal that is a resultant of inversion of the clock signal CLK by an inverter
120
. Namely, an even-numbered sub-stage and an odd-numbered sub-stage are operated in accordance with respective timings so as to have a phase difference of 180°. Each sub-A/D converter carries out the A/D conversion of the input signal of the sub-stage to which the sub-A/D converter belongs so as to determine a predetermined-numbered bit (the n-th bit (n: a predetermined number)) which is outputted to the sub-D/A converter of its sub-stage and the digital error correction circuit
119
. Each sub-D/A converter determines an output voltage in accordance with the difference between an analog input signal voltage of the sub-stage and an analog voltage corresponding to the bit information that has been outputted from the sub-A/D converter, and the output voltage is outputted to the next sub-stage. Thus, each bi
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