Salicided source/drain structure

Details Salicided source/drain structure Salicided source/drain structure

1988-10-31

1989-10-24

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 44, 437 56, 437 57, 437200, 437 27, 357 233, 357 42, 156662, H01L 21265, H01L 270

Patent

active

048762130

ABSTRACT:
A process for fabricating a CMOS device using one sidewall spacer for both the source/drain implant and salicide formation, thereby providing an improved salicided source/drain structure. The use of one sidewall spacer for both the source/drain implant and the silicide formation facilitates the closer spacing of the silicide region to the gate edge. Prior to the salicidation, a silicon overetch is performed to remove the P+ implant in the source/drain and poly regions of the NMOST. The silicon overetch forms a concave surface on the N+ source/drain regions, which allows salicide formation closer to the edge of the channel. Due to the proximity of the edge of the silicide to the edge of the channel, the series resistance of the NMOST is significantly reduced.

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patent: 4599789 (1986-07-01), Gasner
patent: 4642878 (1987-02-01), Maeda
patent: 4682404 (1987-07-01), Miller et al.
patent: 4745086 (1988-05-01), Parrillo et al.
patent: 4753898 (1988-06-01), Parrillo et al.
patent: 4771014 (1988-09-01), Liou et al.

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