Salicide process for forming low sheet resistance doped silicon

Details Salicide process for forming low sheet resistance doped silicon Salicide process for forming low sheet resistance doped silicon

1985-10-25

1987-05-05

Smith, John D.

Coating processes

Electrical product produced

Integrated circuit, printed circuit, or circuit board

156628, 156656, 156657, 427 99, H01L 2124

Patent

active

046631917

ABSTRACT:
A process of forming a patterned silicide layer overlying a processed semiconductor substrate, the substrate having insulator regions and insulator-free regions on an exposed surface thereof, comprising the steps of:

REFERENCES:
patent: 4180596 (1979-12-01), Crowder
patent: 4332839 (1982-06-01), Levinstein
patent: 4337476 (1982-06-01), Fraser
patent: 4389257 (1983-06-01), Geipel
patent: 4470189 (1984-09-01), Roberts
patent: 4563805 (1986-01-01), Scovell
patent: 4567058 (1986-01-01), Koh
patent: 4609568 (1986-09-01), Koh

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