Semiconductor device manufacturing: process – Making passive device – Resistor
Reexamination Certificate
2001-04-25
2003-07-01
Thomas, Tom (Department: 2811)
Semiconductor device manufacturing: process
Making passive device
Resistor
C438S330000, C438S583000, C438S649000
Reexamination Certificate
active
06586311
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a method for semiconductor fabrication supervision and optimization.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate dielectric thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the FET, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
Additionally, reducing the size, or scale, of the components of a typical transistor also increases the density, and number, of the transistors that can be produced on a given amount of wafer real estate, lowering the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
However, reducing the size, or scale, of the components of a typical transistor also requires being able to form and pattern components such as the gate conductor and gate dielectric on such reduced scales, consistently, robustly and reproducibly, preferably in a self-aligned manner. Moreover, reducing the channel length of a transistor also requires reducing the size and area of electrical contacts to active areas, such as N
+
(P
+
) source/drain regions and a doped-polycrystalline silicon (doped-polysilicon or doped-poly) gate conductor. As the size and area of the electrical contacts to the active areas get smaller, the active area contact resistance increases. Increased active area contact resistance is undesirable for a number of reasons. For example, increased active area contact resistance may reduce device drive current, and source/drain current through the device, and may also adversely affect the overall speed and operation of the transistor.
Typically, depositing titanium (Ti) or cobalt (Co) on the active area electrical contacts may decrease active area contact resistance. The cobalt (Co) may then be silicided by annealing with a heat-treatment to form cobalt silicide (CoSi
2
) at the active area electrical contacts (self-aligned silicidation or salicidation). The salicided CoSi
2
lowers active area contact resistance.
As shown in
FIG. 1
, a metal oxide semiconductor field effect transistor (MOSFET or MOS transistor)
100
may be formed on a semiconducting substrate
105
, such as doped-silicon. The MOS transistor
100
may have a doped-poly gate
115
formed above a gate dielectric
110
formed above the semiconducting substrate
105
. The doped-poly gate
115
and the gate dielectric
110
may be separated from N
+
-doped (P
+
-doped) source/drain regions
120
of the MOS transistor
100
by dielectric spacers
125
. The dielectric spacers
125
may be formed above N
−
-doped (P
−
-doped) source drain extension (SDE) regions
130
.
The N
−
-doped (P
−
-doped) source drain extension (SDE) regions
130
are typically provided to reduce the magnitude of the maximum channel electric field found close to the N
+
-doped (P
+
-doped) source/drain regions
120
of the MOS transistor
100
, and, thereby, to reduce the associated hot-carrier effects. The lower (or lighter) doping of the N
−
-doped (P
−
-doped) source drain extension (SDE) regions
130
, relative to the N
+
-doped (P
+
-doped) source/drain regions
120
of the MOS transistor
100
, reduces the magnitude of the maximum channel electric field found close to the N
+
-doped (P
+
-doped) source/drain regions
120
of the MOS transistor
100
, but increases the source-to-drain resistances of the N
−
-doped (P
−
-doped) source drain extension (SDE) regions
130
.
As shown in
FIG. 2
, a cobalt (Co) metal layer
235
may be blanket-deposited on the MOS transistor
100
shown in
FIG. 1
, following a pre-cleaning dip performed to remove residual dielectric material from areas to be salicided. The cobalt (Co) metal layer
235
may then be subjected to an initial rapid thermal anneal (RTA) process performed at a temperature ranging from approximately 450-800° C. for a time ranging from approximately 15-60 seconds. At surfaces
240
of active areas
245
, such as the N
+
-doped (P
+
-doped) source/drain regions
120
and the doped-poly gate
115
, exposed silicon (Si) reacts upon heating with the cobalt (Co) metal layer
235
to form cobalt silicide (CoSi
2
) at the surfaces
240
of the active areas
245
. The cobalt (Co) metal layer
235
is not believed to react with the dielectric spacers
125
upon heating.
As shown in
FIG. 3
, a wet chemical strip of the cobalt (Co) metal layer
235
removes excess, unreacted portions (not shown) of the cobalt (Co) metal layer
235
, leaving behind the salicided cobalt silicide (CoSi
2
)
350
only at and below the surfaces
240
of the active areas
245
. The salicided cobalt silicide (CoSi
2
)
350
may then be subjected to a final rapid thermal anneal (RTA) process performed at a temperature ranging from approximately 600-1000° C. for a time ranging from approximately 10-60 seconds.
Unsalicided resistors have found many applications in complementary metal oxide silicon (CMOS) semiconductor technology. For example, a layer of polysilicon disposed in a semiconducting substrate may form a portion of a resistor. However, unless protected by an overlying salicide block, the layer of polysilicon disposed in the semiconducting substrate would become silicided during a subsequent salicidation process, as described above. The silicidation of the layer of polysilicon would render the resistor much less resistive. Consequently, a conventional salicide block formed of a single layer of silicon dioxide (SiO
2
) or tetraortho silicate (TEOS) is typically formed above such a resistor. However, in the formation of conventional salicide blocks, there is little selectivity to field oxide and/or silicon (Si) during the salicide block etch, performed to form the salicide block. Since an overetch is typically performed (to ensure substantially complete removal of extraneous salicide block material for increased salicidation in other areas of the workpiece), the silicon (Si) loss and/or the field oxide loss can be very significant, particularly in silicon-on-insulator (SOI) applications. In silicon-on-insulator (SOI) applications, the silicon (Si) film and/or the field oxide thickness are much less than in “bulk” applications.
Conventional semiconductor devices may be referred to as “bulk” devices, because bulk devices include a substantially monocrystalline semiconducting bulk substrate in which the active and/or passive circuit elements are disposed. More recently, silicon-on-insulator (SOI) devices have been introduced that consume less power than do bulk devices, an important advantage in many applications such as battery-powered mobile telephones and battery-powered laptop computers. Also, silicon-on-insulator (SOI) devices advantageously operate at higher speeds than do bulk devices.
Silicon-on-insulator (SOI) devices may be characterized by having a thin layer of insulating dielectric material (for example, a buried oxide or nitride or other suitable insulating layer) sandwiched between a bulk semiconducting substrate and the circuit elements of the device. Typically, no other layers of material are interposed between the buried dielectric layer and the bulk substrate. As used herein, th
Owens Douglas W.
Thomas Tom
William, Morgan & Amerson
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