Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With peripheral feature due to separation of smaller...
Reexamination Certificate
1999-01-21
2002-04-02
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With peripheral feature due to separation of smaller...
C257S619000, C438S462000
Reexamination Certificate
active
06365958
ABSTRACT:
The present invention relates generally to semiconductor circuit devices and in particular to the fabrication of semiconductor circuit chips protected against potential damage sometimes caused by the propagation of cracks initiated by the step of separating semiconductor wafers into individual chips.
BACKGROUND OF THE INVENTION
With most semiconductor products, for example integrated circuits, transistors and diodes, a large number of elements are manufactured simultaneously on a large semiconductor wafer of silicon, gallium arsenide, gallium phosphide etc. The semiconductor industry employs the terms “dicing technologies” or “scribing technologies” to refer to those techniques for obtaining a large number of functional chips, or dies, from each semiconductor wafer, Two dicing methods are particularly well known in the art: The grinding-cutting method, using a blade or wire saw, and the scribing method, using a diamond point. Modern silicon technology prefers the cutting method using high-speed rotating blades. When laying out the pattern of circuit chips, or dies, on the surface of the semiconductor wafer, manufacturing efficiency requires to minimize the distance between adjacent circuit chips so that the number of obtainable chips, this means the production yield, can be maximized.
The technology of dicing has been developed to a high standard. In U.S. Pat. No. 4,610,079 of Sep. 9, 1986 (Abe et al., “Method of Dicing a Semiconductor Wafer”) it has been pointed out that three restrictions exist with respect to the minimum distance permissible between adjacent chips. The first restriction is the actual dicing width, the second restriction is the degree of precision to which the cutting machine can be adjusted, and the third restriction is the cracks and chip-outs extending extending laterally from the dicing line into the semiconductor and insulating materials. Even today, the third of these restrictions, namely the generation of cracks, creates the most significant limitation with respect to minimizing the distance between adjacent circuit chips. In addition, those cracks represent significant reliability risks, since they tend to grow and widen under thermal and mechanical stress and thus eventually imperil the functionality of the integrated circuit.
Several solutions have been proposed to solve some of these technical problems associated with the manufacture and dicing of semiconductor wafers. The sealing of dicing streets against penetration of mobile ions with the help of metal edge barriers overlapping insulating layers was proposed in U.S. Pat. No. 4,364.078 of December 1982 (Smith et al., “Edge Barrier of Polysilicon and Metal for Integrated Circuit Chips”) and U.S. Pat. No. 4,656.055 of April 1987 (Dwyer, “Double Level Metal Edge Seal for a Semiconductor Device”). These structures proved ineffective against cracks when insulators extend into the dicing lines and are subject to cracks during the dicing process. In U.S. Pat. No. 5,024,970 of June 1991 (Mori, “Method of Obtaining Semiconductor Chips”), small grooves are obtained in the insulating zone by plasma etching. Many cracks originating from the dicing process are seen to stop at these grooves, but not all of them.
Forming consecutive grooves of different widths by using diamond and resin blades has been described in U.S. Pat. No. 5,266,528 of November 1993 (Yamada et al., “Method od Dicing Semiconductor Wafer with Diamond and Resin Blades”). Dicing line features to limit the spreading of cracks and chip-outs generated during dicing have been proposed in U.S. Pat. No. 4,610,079 of September 1986, mentioned above. Avoiding residues of layers of non-uniform thicknesses, or the generation of lose particles, has been described in U.S. Pat. No. 5,136,354 of August 1992 (Niorita et al., “Semiconductor Device Wafer with Interlayer Insulating Film Covering the Scribe Lines”) with added division in U.S. Pat. No. 5,237,199 of August 1993. In these patents, the etching of slit grooves in passivation films is described in order to stop cracks in the passivation layers during the dicing process.
The latter ideas were continued and elaborated in U.S. Pat. No. 5,414,297 of May 1995 (Mtorita et al., “Semiconductor Device Chip with Interlayer Insulating Film Covering the Scribe Lines”). In particular, it is described how the processes used in forming the conductive interconnections between elements of the integrated circuit can be exploited to generate one vertical metal line parallel to the dicing lines so that it extends around the entire periphery of each integrated circuit chip.
Practical semiconductor manufacturing has demonstrated, however, that these structures do not stop severe cracks originating in the dicing process. On the contrary, thermomechanical stresses generated by modern device applications, board attach processes, or rigorous environmental testing procedures may convey enough energy to many cracks so that they will eventually bypass obstacles or break through a single seal. Following these cracks, moisture and contamination are free to penetrate active circuitry and to start degrading the electrical device performance drastically.
In summary, the goal of providing a technology for dicing semiconductor wafers with assured protection against mechanical and environmental damages and thus offering for the commercial and military markets cost-effective and reliable semiconductor products, manufactured in high volume and with flexible, low-cost design and production methods, has remained elusive, until now.
SUMMARY OF THE INVENTION
According to the Griffith energy-balance concept for crack formation in brittle solids (first published in 1920), a change in the length of a nascent crack or notch cannot change the sum of all energies; in other words, the sum of surface energy and mechanical energy has to stay constant. This means for a crack extension that the surface energy may generally increase, but the mechanical energy has to decrease. The mechanical energy itself consists of the sum of the strain potential energy stored in the material and the potential energy of the outer applied loading system. This says, whenever any of these energies can assume a lower value, the freed energy can be invested in generating more surface for an expanding crack.
Applying the Griffith equilibrium requirement to semiconductor devices, whenever uniform stress is applied (for instance during operation or testing of the semiconductor device) so that it is larger than the failure stress, a nascent crack may propagate spontaneously and without limit—unless it is stopped or arrested. The failure stress at the crack front, in turn, is proportional to the free surface energy per unit area and to Young's modulus (a material constant), and inverse proportional to the length of the starter crack or notch. Since dicing streets are well-known areas for the generation of microcracks, they are prime concerns for latent failures of the semiconductor device due to propagating cracks.
The present invention comprises sacrificial structures for arresting insulator cracks in semiconductor circuit chips and methods for fabricating reinforced insulators in semiconductor wafers. It has particular application to dicing multilevel metal semiconductor wafers into individual circuit chips. The invention permits the introduction of electrically advantageous, but mechanically brittle insulators into the production of large-area, high-speed integrated circuits without risking reliability degradation through propagating cracks initiated by the dicing process.
Based on the invention, the fabrication of more than one metallic sacrificial structure transforms the brittle insulator areas around each circuit chip into reinforced composites with considerable toughness against fracture and propagation of nascent cracks. The main contribution to this toughness comes from the intrinsic adhesion energies of the components. The toughening is attributable to shielding processes, notably bridging, where the reinforcing phases are left intact as ligaments at the crack i
Edwards Darvin R.
Hotchkiss Gregory B.
Ibnabdeljalil M'hamed
Cao Phat X.
Honeycutt Gary C.
Navarro Arthur I.
Telecky Fred
Texas Instruments Incorporated
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